commit 2e9e98d66dc228ebc6257eb33c19c711ab814928
author Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Mon Dec 05 16:55:11 2022 +0900
committer Cra2yPierr0t <uchiyama.kazuhide@gmail.com> Mon Dec 05 16:55:11 2022 +0900
tree 86b4a85edd4187cb530e0627a8d61d32068cf2e2
parent cc01e9a20f5199ae6256157c7ac5add025096747

removed json config

openlane/computer/config.json

diff --git a/openlane/computer/config.json b/openlane/computer/config.json
deleted file mode 100644
index ae2af62..0000000
--- a/openlane/computer/config.json
+++ /dev/null
@@ -1,50 +0,0 @@
-{
-    "DESIGN_NAME": "computer",
-    "DESIGN_IS_CORE": 0,
-    "VERILOG_FILES": [
-      "dir::../../verilog/rtl/defines.v", 
-      "dir::../../verilog/rtl/jacaranda-8/UART/*.v",
-      "dir::../../verilog/rtl/jacaranda-8/*.v"
-    ],
-    "CLOCK_PERIOD": 500,
-    "CLOCK_PORT": "wb_clk_i",
-    "CLOCK_NET": "wb_clk_i",
-    "FP_SIZING": "absolute",
-    "DIE_AREA": "0 0 1500 1500",
-    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
-    "PL_BASIC_PLACEMENT": 0,
-    "PL_TARGET_DENSITY": 0.40,
-    "VDD_NETS": ["vccd1"],
-    "GND_NETS": ["vssd1"],
-    "DIODE_INSERTION_STRATEGY": 4,
-    "RUN_CVC": 1,
-    "ROUTING_CORES": 16,
-    "pdk::sky130*": {
-        "FP_CORE_UTIL": 45,
-        "RT_MAX_LAYER": "met4",
-        "scl::sky130_fd_sc_hd": {
-            "CLOCK_PERIOD": 10
-        },
-        "scl::sky130_fd_sc_hdll": {
-            "CLOCK_PERIOD": 10
-        },
-        "scl::sky130_fd_sc_hs": {
-            "CLOCK_PERIOD": 8
-        },
-        "scl::sky130_fd_sc_ls": {
-            "CLOCK_PERIOD": 10,
-            "SYNTH_MAX_FANOUT": 5
-        },
-        "scl::sky130_fd_sc_ms": {
-            "CLOCK_PERIOD": 10
-        }
-    },
-    "pdk::gf180mcuC": {
-        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
-        "CLOCK_PERIOD": 24.0,
-        "FP_CORE_UTIL": 40,
-        "RT_MAX_LAYER": "Metal4",
-        "SYNTH_MAX_FANOUT": 4,
-        "PL_TARGET_DENSITY": 0.45
-    }
-}