commit: 3cd2964c3cab6c25f37191347649e1e704d5542e
[log]
author: Russell L Friesenhahn <russellf@utexas.edu>
Mon Dec 05 23:54:09 2022 -0600
committer: Russell L Friesenhahn <russellf@utexas.edu>
Mon Dec 05 23:54:09 2022 -0600
tree: 4e93b58c2fbfbbd7e3753a2c8538a0a76dab2354
parent: 90e5d115575c99913c33b9bbb6b32de3c6e0f379 [diff]

Update clock submodule to include spi additions

verilog/rtl/vga-clock[diff]

1 file changed

tree: 4e93b58c2fbfbbd7e3753a2c8538a0a76dab2354

README.md

VGA Clock for GF180

VGA clock info: https://www.zerotoasiccourse.com/post/vga_clock/
VGA clock RTL: https://github.com/mattvenn/vga-clock
PCB https://github.com/mattvenn/vga_clock_pcb