Update clock submodule to include spi additions
diff --git a/verilog/rtl/vga-clock b/verilog/rtl/vga-clock index 94d7b8b..dc48ff5 160000 --- a/verilog/rtl/vga-clock +++ b/verilog/rtl/vga-clock
@@ -1 +1 @@ -Subproject commit 94d7b8b5b98ed4509907fc7daea14dee0f13da8e +Subproject commit dc48ff5f7ac585e9de196eaed707fd5167019185