)]}'
{
  "commit": "3cd2964c3cab6c25f37191347649e1e704d5542e",
  "tree": "4e93b58c2fbfbbd7e3753a2c8538a0a76dab2354",
  "parents": [
    "90e5d115575c99913c33b9bbb6b32de3c6e0f379"
  ],
  "author": {
    "name": "Russell L Friesenhahn",
    "email": "russellf@utexas.edu",
    "time": "Mon Dec 05 23:54:09 2022 -0600"
  },
  "committer": {
    "name": "Russell L Friesenhahn",
    "email": "russellf@utexas.edu",
    "time": "Mon Dec 05 23:54:09 2022 -0600"
  },
  "message": "Update clock submodule to include spi additions\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "94d7b8b5b98ed4509907fc7daea14dee0f13da8e",
      "old_mode": 57344,
      "old_path": "verilog/rtl/vga-clock",
      "new_id": "dc48ff5f7ac585e9de196eaed707fd5167019185",
      "new_mode": 57344,
      "new_path": "verilog/rtl/vga-clock"
    }
  ]
}