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foss-eda-tools / third_party / shuttle / gf180mcu / mpw-000 / slot-001 / ff8b94f1db13086520f5d5b5cd8b2a298abb28dd
commitff8b94f1db13086520f5d5b5cd8b2a298abb28dd[log] [tgz]
authorGreg Davill <greg.davill@gmail.com>Sun Dec 04 02:29:33 2022 +1030
committerGreg Davill <greg.davill@gmail.com>Sun Dec 04 02:29:33 2022 +1030
tree94056fdd6f5953a652671acc171ed60c77a26b1d
parent658681205a417ba0643f9264740bf2774a77e6ef [diff]
rtl: Use specific cells for scanchain

- Add RAM IP block for RF/CSR storage
10 files changed
tree: 94056fdd6f5953a652671acc171ed60c77a26b1d
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. scripts/
  10. sdc/
  11. sdf/
  12. signoff/
  13. spef/
  14. spi/
  15. verilog/
  16. .gitignore
  17. .gitmodules
  18. configure.py
  19. info.yaml
  20. LICENSE
  21. Makefile
  22. README.md
README.md

GF180 MPW0 Serv

An award winning CPU design fit into the GF180 MPW0 Shuttle.

To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.

Another I/O pin is responsible for handling clock and reset. Operation will run as follows:

  1. Using an external controller, load in default values for the wishbone bus, bring serv out of reset and clock it.
  2. Latch in and scan out the wishbone bus values. Handle any requests.
  3. Scan in data from the request and clock serv.
  4. Goto 2.

In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.