commit | 658681205a417ba0643f9264740bf2774a77e6ef | [log] [tgz] |
---|---|---|
author | Greg Davill <greg.davill@gmail.com> | Sat Dec 03 22:13:10 2022 +1030 |
committer | Greg Davill <greg.davill@gmail.com> | Sat Dec 03 22:13:10 2022 +1030 |
tree | 37f7207e07e753f11fa3ab19ae8c1462a18459c0 | |
parent | 7cdc71e4b0e2647f85081182fef88ea5140317bf [diff] |
ci: Update cache key
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.