commit | 7cdc71e4b0e2647f85081182fef88ea5140317bf | [log] [tgz] |
---|---|---|
author | Greg Davill <greg.davill@gmail.com> | Sat Dec 03 22:03:22 2022 +1030 |
committer | Greg Davill <greg.davill@gmail.com> | Sat Dec 03 22:03:22 2022 +1030 |
tree | de69db3114bca57da4ee7919f75d5d497bf05dcd | |
parent | 796f1870650384b57af0c0c266233ec291965e20 [diff] |
openlane: Update to gfmwp-0d
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.