blob: 31ca2b2f3b06b360416564b6c2980f6329d54644 [file] [log] [blame]
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "tiny_user_project")
(DATE "Sun Dec 4 07:57:20 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
(DIVIDER .)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "tiny_user_project")
(INSTANCE)
(DELAY
(ABSOLUTE
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(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[45\].SE (7.635:7.635:7.635) (4.831:4.831:4.831))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[44\].SE (7.629:7.629:7.629) (4.825:4.825:4.825))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[51\].SE (7.636:7.636:7.636) (4.831:4.831:4.831))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[50\].SE (7.552:7.552:7.552) (4.748:4.748:4.748))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[49\].SE (7.635:7.635:7.635) (4.831:4.831:4.831))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[48\].SE (7.635:7.635:7.635) (4.831:4.831:4.831))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[47\].SE (7.635:7.635:7.635) (4.831:4.831:4.831))
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(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[36\].SE (7.658:7.658:7.658) (4.853:4.853:4.853))
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(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[34\].SE (7.656:7.656:7.656) (4.851:4.851:4.851))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[37\].SE (7.651:7.651:7.651) (4.846:4.846:4.846))
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(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[32\].SE (7.660:7.660:7.660) (4.855:4.855:4.855))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[31\].SE (7.659:7.659:7.659) (4.854:4.854:4.854))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[30\].SE (7.659:7.659:7.659) (4.855:4.855:4.855))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[29\].SE (7.660:7.660:7.660) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[13\].SE (7.659:7.659:7.659) (4.854:4.854:4.854))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[28\].SE (7.660:7.660:7.660) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[27\].SE (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[26\].SE (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[25\].SE (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[24\].SE (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[23\].SE (7.661:7.661:7.661) (4.857:4.857:4.857))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[22\].SE (7.665:7.665:7.665) (4.860:4.860:4.860))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[15\].SE (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[16\].SE (7.655:7.655:7.655) (4.850:4.850:4.850))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[9\].SE (7.666:7.666:7.666) (4.861:4.861:4.861))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[8\].SE (7.667:7.667:7.667) (4.862:4.862:4.862))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[7\].SE (7.668:7.668:7.668) (4.863:4.863:4.863))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[6\].SE (7.668:7.668:7.668) (4.864:4.864:4.864))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[18\].SE (7.610:7.610:7.610) (4.805:4.805:4.805))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[11\].SE (7.668:7.668:7.668) (4.864:4.864:4.864))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[19\].SE (7.610:7.610:7.610) (4.805:4.805:4.805))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[17\].SE (7.655:7.655:7.655) (4.850:4.850:4.850))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[20\].SE (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[12\].SE (7.662:7.662:7.662) (4.857:4.857:4.857))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[21\].SE (7.664:7.664:7.664) (4.859:4.859:4.859))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[14\].SE (7.659:7.659:7.659) (4.854:4.854:4.854))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[10\].SE (7.665:7.665:7.665) (4.860:4.860:4.860))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[52\].SE (7.552:7.552:7.552) (4.748:4.748:4.748))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[53\].SE (7.552:7.552:7.552) (4.748:4.748:4.748))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[42\].SE (7.619:7.619:7.619) (4.815:4.815:4.815))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[43\].SE (7.625:7.625:7.625) (4.821:4.821:4.821))
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(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[41\].SE (7.611:7.611:7.611) (4.807:4.807:4.807))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[0\].SE (7.592:7.592:7.592) (4.788:4.788:4.788))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[1\].SE (7.609:7.609:7.609) (4.805:4.805:4.805))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[2\].SE (7.609:7.609:7.609) (4.804:4.804:4.804))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[39\].SE (7.602:7.602:7.602) (4.798:4.798:4.798))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[5\].SE (7.669:7.669:7.669) (4.864:4.864:4.864))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[4\].SE (7.669:7.669:7.669) (4.864:4.864:4.864))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[3\].SE (7.669:7.669:7.669) (4.864:4.864:4.864))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[38\].SE (7.598:7.598:7.598) (4.793:4.793:4.793))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[54\].SE (7.552:7.552:7.552) (4.748:4.748:4.748))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[55\].SE (7.551:7.551:7.551) (4.747:4.747:4.747))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[56\].SE (7.551:7.551:7.551) (4.747:4.747:4.747))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[62\].SE (7.561:7.561:7.561) (4.757:4.757:4.757))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[61\].SE (7.563:7.563:7.563) (4.759:4.759:4.759))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[60\].SE (7.536:7.536:7.536) (4.732:4.732:4.732))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[59\].SE (7.534:7.534:7.534) (4.730:4.730:4.730))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[58\].SE (7.550:7.550:7.550) (4.746:4.746:4.746))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[57\].SE (7.551:7.551:7.551) (4.747:4.747:4.747))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[65\].SE (7.561:7.561:7.561) (4.757:4.757:4.757))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[64\].SE (7.569:7.569:7.569) (4.765:4.765:4.765))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[63\].SE (7.560:7.560:7.560) (4.756:4.756:4.756))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[66\].SE (7.561:7.561:7.561) (4.757:4.757:4.757))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[69\].SE (7.597:7.597:7.597) (4.792:4.792:4.792))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[68\].SE (7.589:7.589:7.589) (4.785:4.785:4.785))
(INTERCONNECT io_in[11] mod\.u_scanchain_local\.scan_flop\[67\].SE (7.587:7.587:7.587) (4.782:4.782:4.782))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[67\]_SE.I (7.580:7.580:7.580) (4.776:4.776:4.776))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[68\]_SE.I (7.583:7.583:7.583) (4.779:4.779:4.779))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[69\]_SE.I (7.601:7.601:7.601) (4.797:4.797:4.797))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[66\]_SE.I (7.572:7.572:7.572) (4.768:4.768:4.768))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[63\]_SE.I (7.560:7.560:7.560) (4.756:4.756:4.756))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[64\]_SE.I (7.567:7.567:7.567) (4.763:4.763:4.763))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[65\]_SE.I (7.561:7.561:7.561) (4.757:4.757:4.757))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[57\]_SE.I (7.548:7.548:7.548) (4.744:4.744:4.744))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[58\]_SE.I (7.547:7.547:7.547) (4.743:4.743:4.743))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[59\]_SE.I (7.529:7.529:7.529) (4.725:4.725:4.725))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[60\]_SE.I (7.542:7.542:7.542) (4.738:4.738:4.738))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[61\]_SE.I (7.556:7.556:7.556) (4.752:4.752:4.752))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[62\]_SE.I (7.560:7.560:7.560) (4.756:4.756:4.756))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[56\]_SE.I (7.551:7.551:7.551) (4.747:4.747:4.747))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[55\]_SE.I (7.551:7.551:7.551) (4.747:4.747:4.747))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[54\]_SE.I (7.551:7.551:7.551) (4.747:4.747:4.747))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[38\]_SE.I (7.597:7.597:7.597) (4.793:4.793:4.793))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[3\]_SE.I (7.669:7.669:7.669) (4.864:4.864:4.864))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[4\]_SE.I (7.669:7.669:7.669) (4.864:4.864:4.864))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[5\]_SE.I (7.668:7.668:7.668) (4.864:4.864:4.864))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[39\]_SE.I (7.602:7.602:7.602) (4.798:4.798:4.798))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[2\]_SE.I (7.609:7.609:7.609) (4.805:4.805:4.805))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[1\]_SE.I (7.609:7.609:7.609) (4.805:4.805:4.805))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[0\]_SE.I (7.592:7.592:7.592) (4.788:4.788:4.788))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[41\]_SE.I (7.611:7.611:7.611) (4.807:4.807:4.807))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[40\]_SE.I (7.604:7.604:7.604) (4.799:4.799:4.799))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[43\]_SE.I (7.623:7.623:7.623) (4.818:4.818:4.818))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[42\]_SE.I (7.618:7.618:7.618) (4.814:4.814:4.814))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[53\]_SE.I (7.552:7.552:7.552) (4.748:4.748:4.748))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[52\]_SE.I (7.552:7.552:7.552) (4.748:4.748:4.748))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[10\]_SE.I (7.665:7.665:7.665) (4.860:4.860:4.860))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[14\]_SE.I (7.659:7.659:7.659) (4.855:4.855:4.855))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[21\]_SE.I (7.665:7.665:7.665) (4.860:4.860:4.860))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[12\]_SE.I (7.664:7.664:7.664) (4.859:4.859:4.859))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[20\]_SE.I (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[17\]_SE.I (7.655:7.655:7.655) (4.851:4.851:4.851))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[19\]_SE.I (7.610:7.610:7.610) (4.805:4.805:4.805))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[11\]_SE.I (7.668:7.668:7.668) (4.863:4.863:4.863))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[18\]_SE.I (7.609:7.609:7.609) (4.805:4.805:4.805))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[6\]_SE.I (7.668:7.668:7.668) (4.863:4.863:4.863))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[7\]_SE.I (7.668:7.668:7.668) (4.863:4.863:4.863))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[8\]_SE.I (7.668:7.668:7.668) (4.863:4.863:4.863))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[9\]_SE.I (7.668:7.668:7.668) (4.863:4.863:4.863))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[16\]_SE.I (7.659:7.659:7.659) (4.854:4.854:4.854))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[15\]_SE.I (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[22\]_SE.I (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[23\]_SE.I (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[24\]_SE.I (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[25\]_SE.I (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[26\]_SE.I (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[27\]_SE.I (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[28\]_SE.I (7.661:7.661:7.661) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[13\]_SE.I (7.659:7.659:7.659) (4.855:4.855:4.855))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[29\]_SE.I (7.660:7.660:7.660) (4.856:4.856:4.856))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[30\]_SE.I (7.659:7.659:7.659) (4.855:4.855:4.855))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[31\]_SE.I (7.660:7.660:7.660) (4.855:4.855:4.855))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[32\]_SE.I (7.659:7.659:7.659) (4.855:4.855:4.855))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[33\]_SE.I (7.653:7.653:7.653) (4.848:4.848:4.848))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[37\]_SE.I (7.644:7.644:7.644) (4.839:4.839:4.839))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[34\]_SE.I (7.656:7.656:7.656) (4.851:4.851:4.851))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[35\]_SE.I (7.657:7.657:7.657) (4.852:4.852:4.852))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[36\]_SE.I (7.658:7.658:7.658) (4.853:4.853:4.853))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[46\]_SE.I (7.634:7.634:7.634) (4.830:4.830:4.830))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[47\]_SE.I (7.635:7.635:7.635) (4.830:4.830:4.830))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[48\]_SE.I (7.635:7.635:7.635) (4.831:4.831:4.831))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[49\]_SE.I (7.552:7.552:7.552) (4.748:4.748:4.748))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[50\]_SE.I (7.552:7.552:7.552) (4.748:4.748:4.748))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[51\]_SE.I (7.552:7.552:7.552) (4.748:4.748:4.748))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[44\]_SE.I (7.632:7.632:7.632) (4.828:4.828:4.828))
(INTERCONNECT io_in[11] ANTENNA_mod\.u_scanchain_local\.scan_flop\[45\]_SE.I (7.632:7.632:7.632) (4.828:4.828:4.828))
(INTERCONNECT io_in[12] _2594_.CLK (19.780:19.780:19.780) (12.554:12.554:12.554))
(INTERCONNECT io_in[12] _2620_.CLK (19.779:19.779:19.779) (12.552:12.552:12.552))
(INTERCONNECT io_in[12] _2619_.CLK (19.784:19.784:19.784) (12.557:12.557:12.557))
(INTERCONNECT io_in[12] _2618_.CLK (19.786:19.786:19.786) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] _2617_.CLK (19.782:19.782:19.782) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] _2609_.CLK (19.785:19.785:19.785) (12.559:12.559:12.559))
(INTERCONNECT io_in[12] _2608_.CLK (19.786:19.786:19.786) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] _2607_.CLK (19.786:19.786:19.786) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] _2592_.CLK (19.785:19.785:19.785) (12.559:12.559:12.559))
(INTERCONNECT io_in[12] _2591_.CLK (19.786:19.786:19.786) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] _2590_.CLK (19.786:19.786:19.786) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] _2610_.CLK (19.783:19.783:19.783) (12.557:12.557:12.557))
(INTERCONNECT io_in[12] _2593_.CLK (19.782:19.782:19.782) (12.556:12.556:12.556))
(INTERCONNECT io_in[12] _2665_.CLK (19.478:19.478:19.478) (12.254:12.254:12.254))
(INTERCONNECT io_in[12] _2750_.CLK (19.756:19.756:19.756) (12.530:12.530:12.530))
(INTERCONNECT io_in[12] _2638_.CLK (19.505:19.505:19.505) (12.280:12.280:12.280))
(INTERCONNECT io_in[12] _2666_.CLK (19.434:19.434:19.434) (12.210:12.210:12.210))
(INTERCONNECT io_in[12] _2667_.CLK (19.405:19.405:19.405) (12.182:12.182:12.182))
(INTERCONNECT io_in[12] _2703_.CLK (19.344:19.344:19.344) (12.121:12.121:12.121))
(INTERCONNECT io_in[12] _2706_.CLK (19.323:19.323:19.323) (12.100:12.100:12.100))
(INTERCONNECT io_in[12] _2705_.CLK (19.329:19.329:19.329) (12.105:12.105:12.105))
(INTERCONNECT io_in[12] _2704_.CLK (19.329:19.329:19.329) (12.105:12.105:12.105))
(INTERCONNECT io_in[12] _2702_.CLK (19.352:19.352:19.352) (12.129:12.129:12.129))
(INTERCONNECT io_in[12] _2668_.CLK (19.394:19.394:19.394) (12.170:12.170:12.170))
(INTERCONNECT io_in[12] _2669_.CLK (19.372:19.372:19.372) (12.149:12.149:12.149))
(INTERCONNECT io_in[12] _2792_.CLK (19.489:19.489:19.489) (12.265:12.265:12.265))
(INTERCONNECT io_in[12] _2774_.CLK (19.560:19.560:19.560) (12.336:12.336:12.336))
(INTERCONNECT io_in[12] _2773_.CLK (19.560:19.560:19.560) (12.336:12.336:12.336))
(INTERCONNECT io_in[12] _2646_.CLK (19.477:19.477:19.477) (12.253:12.253:12.253))
(INTERCONNECT io_in[12] _2645_.CLK (19.475:19.475:19.475) (12.251:12.251:12.251))
(INTERCONNECT io_in[12] _2789_.CLK (19.472:19.472:19.472) (12.248:12.248:12.248))
(INTERCONNECT io_in[12] _2647_.CLK (19.480:19.480:19.480) (12.256:12.256:12.256))
(INTERCONNECT io_in[12] _2788_.CLK (19.480:19.480:19.480) (12.256:12.256:12.256))
(INTERCONNECT io_in[12] _2787_.CLK (19.489:19.489:19.489) (12.265:12.265:12.265))
(INTERCONNECT io_in[12] _2786_.CLK (19.484:19.484:19.484) (12.260:12.260:12.260))
(INTERCONNECT io_in[12] _2644_.CLK (19.490:19.490:19.490) (12.266:12.266:12.266))
(INTERCONNECT io_in[12] _2790_.CLK (19.480:19.480:19.480) (12.256:12.256:12.256))
(INTERCONNECT io_in[12] _2640_.CLK (19.501:19.501:19.501) (12.277:12.277:12.277))
(INTERCONNECT io_in[12] _2783_.CLK (19.492:19.492:19.492) (12.268:12.268:12.268))
(INTERCONNECT io_in[12] _2785_.CLK (19.494:19.494:19.494) (12.270:12.270:12.270))
(INTERCONNECT io_in[12] _2784_.CLK (19.503:19.503:19.503) (12.279:12.279:12.279))
(INTERCONNECT io_in[12] _2779_.CLK (19.503:19.503:19.503) (12.279:12.279:12.279))
(INTERCONNECT io_in[12] _2642_.CLK (19.497:19.497:19.497) (12.273:12.273:12.273))
(INTERCONNECT io_in[12] _2782_.CLK (19.497:19.497:19.497) (12.272:12.272:12.272))
(INTERCONNECT io_in[12] _2781_.CLK (19.502:19.502:19.502) (12.278:12.278:12.278))
(INTERCONNECT io_in[12] _2780_.CLK (19.503:19.503:19.503) (12.279:12.279:12.279))
(INTERCONNECT io_in[12] _2772_.CLK (19.536:19.536:19.536) (12.311:12.311:12.311))
(INTERCONNECT io_in[12] _2771_.CLK (19.536:19.536:19.536) (12.312:12.312:12.312))
(INTERCONNECT io_in[12] _2664_.CLK (19.508:19.508:19.508) (12.284:12.284:12.284))
(INTERCONNECT io_in[12] _2663_.CLK (19.521:19.521:19.521) (12.297:12.297:12.297))
(INTERCONNECT io_in[12] _2791_.CLK (19.470:19.470:19.470) (12.246:12.246:12.246))
(INTERCONNECT io_in[12] _2649_.CLK (19.479:19.479:19.479) (12.255:12.255:12.255))
(INTERCONNECT io_in[12] _2648_.CLK (19.459:19.459:19.459) (12.235:12.235:12.235))
(INTERCONNECT io_in[12] _2775_.CLK (19.538:19.538:19.538) (12.314:12.314:12.314))
(INTERCONNECT io_in[12] _2769_.CLK (19.538:19.538:19.538) (12.313:12.313:12.313))
(INTERCONNECT io_in[12] _2778_.CLK (19.538:19.538:19.538) (12.314:12.314:12.314))
(INTERCONNECT io_in[12] _2636_.CLK (19.507:19.507:19.507) (12.283:12.283:12.283))
(INTERCONNECT io_in[12] _2767_.CLK (19.538:19.538:19.538) (12.313:12.313:12.313))
(INTERCONNECT io_in[12] _2764_.CLK (19.538:19.538:19.538) (12.314:12.314:12.314))
(INTERCONNECT io_in[12] _2635_.CLK (19.538:19.538:19.538) (12.314:12.314:12.314))
(INTERCONNECT io_in[12] _2768_.CLK (19.507:19.507:19.507) (12.283:12.283:12.283))
(INTERCONNECT io_in[12] _2770_.CLK (19.536:19.536:19.536) (12.312:12.312:12.312))
(INTERCONNECT io_in[12] _2708_.CLK (19.280:19.280:19.280) (12.057:12.057:12.057))
(INTERCONNECT io_in[12] _2672_.CLK (19.353:19.353:19.353) (12.129:12.129:12.129))
(INTERCONNECT io_in[12] _2709_.CLK (19.273:19.273:19.273) (12.050:12.050:12.050))
(INTERCONNECT io_in[12] _2674_.CLK (19.353:19.353:19.353) (12.130:12.130:12.130))
(INTERCONNECT io_in[12] _2661_.CLK (19.545:19.545:19.545) (12.321:12.321:12.321))
(INTERCONNECT io_in[12] _2777_.CLK (19.592:19.592:19.592) (12.368:12.368:12.368))
(INTERCONNECT io_in[12] _2707_.CLK (19.284:19.284:19.284) (12.061:12.061:12.061))
(INTERCONNECT io_in[12] _2673_.CLK (19.353:19.353:19.353) (12.129:12.129:12.129))
(INTERCONNECT io_in[12] _2675_.CLK (19.261:19.261:19.261) (12.038:12.038:12.038))
(INTERCONNECT io_in[12] _2710_.CLK (19.265:19.265:19.265) (12.042:12.042:12.042))
(INTERCONNECT io_in[12] _2700_.CLK (19.344:19.344:19.344) (12.121:12.121:12.121))
(INTERCONNECT io_in[12] _2699_.CLK (19.354:19.354:19.354) (12.131:12.131:12.131))
(INTERCONNECT io_in[12] _2698_.CLK (19.354:19.354:19.354) (12.131:12.131:12.131))
(INTERCONNECT io_in[12] _2697_.CLK (19.354:19.354:19.354) (12.131:12.131:12.131))
(INTERCONNECT io_in[12] _2671_.CLK (19.352:19.352:19.352) (12.129:12.129:12.129))
(INTERCONNECT io_in[12] _2670_.CLK (19.344:19.344:19.344) (12.121:12.121:12.121))
(INTERCONNECT io_in[12] _2701_.CLK (19.353:19.353:19.353) (12.129:12.129:12.129))
(INTERCONNECT io_in[12] _2696_.CLK (19.354:19.354:19.354) (12.131:12.131:12.131))
(INTERCONNECT io_in[12] _2680_.CLK (19.184:19.184:19.184) (11.961:11.961:11.961))
(INTERCONNECT io_in[12] _2678_.CLK (19.226:19.226:19.226) (12.003:12.003:12.003))
(INTERCONNECT io_in[12] _2715_.CLK (19.178:19.178:19.178) (11.955:11.955:11.955))
(INTERCONNECT io_in[12] _2679_.CLK (19.198:19.198:19.198) (11.975:11.975:11.975))
(INTERCONNECT io_in[12] _2676_.CLK (19.254:19.254:19.254) (12.031:12.031:12.031))
(INTERCONNECT io_in[12] _2677_.CLK (19.247:19.247:19.247) (12.024:12.024:12.024))
(INTERCONNECT io_in[12] _2711_.CLK (19.255:19.255:19.255) (12.032:12.032:12.032))
(INTERCONNECT io_in[12] _2712_.CLK (19.244:19.244:19.244) (12.022:12.022:12.022))
(INTERCONNECT io_in[12] _2713_.CLK (19.214:19.214:19.214) (11.991:11.991:11.991))
(INTERCONNECT io_in[12] _2714_.CLK (19.180:19.180:19.180) (11.958:11.958:11.958))
(INTERCONNECT io_in[12] _2720_.CLK (19.171:19.171:19.171) (11.948:11.948:11.948))
(INTERCONNECT io_in[12] _2718_.CLK (19.170:19.170:19.170) (11.948:11.948:11.948))
(INTERCONNECT io_in[12] _2717_.CLK (19.170:19.170:19.170) (11.947:11.947:11.947))
(INTERCONNECT io_in[12] _2716_.CLK (19.170:19.170:19.170) (11.947:11.947:11.947))
(INTERCONNECT io_in[12] _2719_.CLK (19.170:19.170:19.170) (11.948:11.948:11.948))
(INTERCONNECT io_in[12] _2682_.CLK (19.198:19.198:19.198) (11.975:11.975:11.975))
(INTERCONNECT io_in[12] _2681_.CLK (19.198:19.198:19.198) (11.975:11.975:11.975))
(INTERCONNECT io_in[12] _2684_.CLK (19.172:19.172:19.172) (11.949:11.949:11.949))
(INTERCONNECT io_in[12] _2683_.CLK (19.198:19.198:19.198) (11.975:11.975:11.975))
(INTERCONNECT io_in[12] _2660_.CLK (19.580:19.580:19.580) (12.356:12.356:12.356))
(INTERCONNECT io_in[12] _2634_.CLK (19.539:19.539:19.539) (12.314:12.314:12.314))
(INTERCONNECT io_in[12] _2762_.CLK (19.593:19.593:19.593) (12.368:12.368:12.368))
(INTERCONNECT io_in[12] _2761_.CLK (19.539:19.539:19.539) (12.314:12.314:12.314))
(INTERCONNECT io_in[12] _2650_.CLK (19.609:19.609:19.609) (12.384:12.384:12.384))
(INTERCONNECT io_in[12] _2658_.CLK (19.737:19.737:19.737) (12.512:12.512:12.512))
(INTERCONNECT io_in[12] _2692_.CLK (19.661:19.661:19.661) (12.436:12.436:12.436))
(INTERCONNECT io_in[12] _2693_.CLK (19.648:19.648:19.648) (12.423:12.423:12.423))
(INTERCONNECT io_in[12] _2659_.CLK (19.603:19.603:19.603) (12.378:12.378:12.378))
(INTERCONNECT io_in[12] _2695_.CLK (19.354:19.354:19.354) (12.131:12.131:12.131))
(INTERCONNECT io_in[12] _2763_.CLK (19.538:19.538:19.538) (12.314:12.314:12.314))
(INTERCONNECT io_in[12] _2662_.CLK (19.541:19.541:19.541) (12.316:12.316:12.316))
(INTERCONNECT io_in[12] _2776_.CLK (19.565:19.565:19.565) (12.341:12.341:12.341))
(INTERCONNECT io_in[12] _2685_.CLK (19.172:19.172:19.172) (11.949:11.949:11.949))
(INTERCONNECT io_in[12] _2689_.CLK (19.738:19.738:19.738) (12.512:12.512:12.512))
(INTERCONNECT io_in[12] _2688_.CLK (19.736:19.736:19.736) (12.511:12.511:12.511))
(INTERCONNECT io_in[12] _2686_.CLK (19.171:19.171:19.171) (11.949:11.949:11.949))
(INTERCONNECT io_in[12] _2687_.CLK (19.736:19.736:19.736) (12.510:12.510:12.510))
(INTERCONNECT io_in[12] _2721_.CLK (19.171:19.171:19.171) (11.949:11.949:11.949))
(INTERCONNECT io_in[12] _2723_.CLK (19.738:19.738:19.738) (12.512:12.512:12.512))
(INTERCONNECT io_in[12] _2722_.CLK (19.171:19.171:19.171) (11.948:11.948:11.948))
(INTERCONNECT io_in[12] _2802_.CLK (19.734:19.734:19.734) (12.508:12.508:12.508))
(INTERCONNECT io_in[12] _2800_.CLK (19.636:19.636:19.636) (12.411:12.411:12.411))
(INTERCONNECT io_in[12] _2690_.CLK (19.738:19.738:19.738) (12.512:12.512:12.512))
(INTERCONNECT io_in[12] _2804_.CLK (19.734:19.734:19.734) (12.509:12.509:12.509))
(INTERCONNECT io_in[12] _2614_.CLK (19.738:19.738:19.738) (12.512:12.512:12.512))
(INTERCONNECT io_in[12] _2803_.CLK (19.734:19.734:19.734) (12.508:12.508:12.508))
(INTERCONNECT io_in[12] _2801_.CLK (19.738:19.738:19.738) (12.512:12.512:12.512))
(INTERCONNECT io_in[12] _2799_.CLK (19.738:19.738:19.738) (12.513:12.513:12.513))
(INTERCONNECT io_in[12] _2794_.CLK (19.735:19.735:19.735) (12.509:12.509:12.509))
(INTERCONNECT io_in[12] _2724_.CLK (19.624:19.624:19.624) (12.399:12.399:12.399))
(INTERCONNECT io_in[12] _2639_.CLK (19.497:19.497:19.497) (12.273:12.273:12.273))
(INTERCONNECT io_in[12] _2643_.CLK (19.497:19.497:19.497) (12.273:12.273:12.273))
(INTERCONNECT io_in[12] _2747_.CLK (19.802:19.802:19.802) (12.575:12.575:12.575))
(INTERCONNECT io_in[12] _2733_.CLK (19.802:19.802:19.802) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] _2655_.CLK (19.803:19.803:19.803) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] _2653_.CLK (19.802:19.802:19.802) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] _2731_.CLK (19.793:19.793:19.793) (12.566:12.566:12.566))
(INTERCONNECT io_in[12] _2730_.CLK (19.793:19.793:19.793) (12.566:12.566:12.566))
(INTERCONNECT io_in[12] _2735_.CLK (19.787:19.787:19.787) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] _2748_.CLK (19.802:19.802:19.802) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] _2734_.CLK (19.787:19.787:19.787) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] _2656_.CLK (19.802:19.802:19.802) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] _2654_.CLK (19.803:19.803:19.803) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] _2736_.CLK (19.787:19.787:19.787) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] _2758_.CLK (19.803:19.803:19.803) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] _2641_.CLK (19.497:19.497:19.497) (12.273:12.273:12.273))
(INTERCONNECT io_in[12] _2760_.CLK (19.798:19.798:19.798) (12.571:12.571:12.571))
(INTERCONNECT io_in[12] _2766_.CLK (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] _2765_.CLK (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] _2742_.CLK (19.508:19.508:19.508) (12.284:12.284:12.284))
(INTERCONNECT io_in[12] _2743_.CLK (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] _2741_.CLK (19.508:19.508:19.508) (12.284:12.284:12.284))
(INTERCONNECT io_in[12] _2740_.CLK (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] _2739_.CLK (19.798:19.798:19.798) (12.572:12.572:12.572))
(INTERCONNECT io_in[12] _2727_.CLK (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] _2756_.CLK (19.798:19.798:19.798) (12.571:12.571:12.571))
(INTERCONNECT io_in[12] _2728_.CLK (19.796:19.796:19.796) (12.570:12.570:12.570))
(INTERCONNECT io_in[12] _2738_.CLK (19.799:19.799:19.799) (12.572:12.572:12.572))
(INTERCONNECT io_in[12] _2732_.CLK (19.800:19.800:19.800) (12.573:12.573:12.573))
(INTERCONNECT io_in[12] _2729_.CLK (19.794:19.794:19.794) (12.568:12.568:12.568))
(INTERCONNECT io_in[12] _2637_.CLK (19.506:19.506:19.506) (12.282:12.282:12.282))
(INTERCONNECT io_in[12] _2691_.CLK (19.675:19.675:19.675) (12.449:12.449:12.449))
(INTERCONNECT io_in[12] _2757_.CLK (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] _2753_.CLK (19.756:19.756:19.756) (12.530:12.530:12.530))
(INTERCONNECT io_in[12] _2755_.CLK (19.756:19.756:19.756) (12.530:12.530:12.530))
(INTERCONNECT io_in[12] _2737_.CLK (19.797:19.797:19.797) (12.571:12.571:12.571))
(INTERCONNECT io_in[12] _2754_.CLK (19.756:19.756:19.756) (12.530:12.530:12.530))
(INTERCONNECT io_in[12] _2796_.CLK (19.661:19.661:19.661) (12.436:12.436:12.436))
(INTERCONNECT io_in[12] _2759_.CLK (19.797:19.797:19.797) (12.571:12.571:12.571))
(INTERCONNECT io_in[12] _2694_.CLK (19.662:19.662:19.662) (12.436:12.436:12.436))
(INTERCONNECT io_in[12] _2651_.CLK (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] _2625_.CLK (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] _2726_.CLK (19.733:19.733:19.733) (12.507:12.507:12.507))
(INTERCONNECT io_in[12] _2627_.CLK (19.733:19.733:19.733) (12.508:12.508:12.508))
(INTERCONNECT io_in[12] _2797_.CLK (19.732:19.732:19.732) (12.506:12.506:12.506))
(INTERCONNECT io_in[12] _2603_.CLK (19.732:19.732:19.732) (12.507:12.507:12.507))
(INTERCONNECT io_in[12] _2805_.CLK (19.723:19.723:19.723) (12.498:12.498:12.498))
(INTERCONNECT io_in[12] _2798_.CLK (19.691:19.691:19.691) (12.465:12.465:12.465))
(INTERCONNECT io_in[12] _2795_.CLK (19.678:19.678:19.678) (12.453:12.453:12.453))
(INTERCONNECT io_in[12] _2793_.CLK (19.673:19.673:19.673) (12.447:12.447:12.447))
(INTERCONNECT io_in[12] _2587_.CLK (19.733:19.733:19.733) (12.507:12.507:12.507))
(INTERCONNECT io_in[12] _2624_.CLK (19.698:19.698:19.698) (12.473:12.473:12.473))
(INTERCONNECT io_in[12] mod\.u_cpu\.rf_ram\.RAM0.CLK (19.736:19.736:19.736) (12.511:12.511:12.511))
(INTERCONNECT io_in[12] _2725_.CLK (19.736:19.736:19.736) (12.510:12.510:12.510))
(INTERCONNECT io_in[12] _2631_.CLK (19.757:19.757:19.757) (12.531:12.531:12.531))
(INTERCONNECT io_in[12] _2630_.CLK (19.742:19.742:19.742) (12.516:12.516:12.516))
(INTERCONNECT io_in[12] _2633_.CLK (19.744:19.744:19.744) (12.518:12.518:12.518))
(INTERCONNECT io_in[12] _2629_.CLK (19.739:19.739:19.739) (12.513:12.513:12.513))
(INTERCONNECT io_in[12] _2628_.CLK (19.736:19.736:19.736) (12.510:12.510:12.510))
(INTERCONNECT io_in[12] _2626_.CLK (19.734:19.734:19.734) (12.508:12.508:12.508))
(INTERCONNECT io_in[12] _2657_.CLK (19.755:19.755:19.755) (12.529:12.529:12.529))
(INTERCONNECT io_in[12] _2751_.CLK (19.794:19.794:19.794) (12.568:12.568:12.568))
(INTERCONNECT io_in[12] _2749_.CLK (19.756:19.756:19.756) (12.530:12.530:12.530))
(INTERCONNECT io_in[12] _2752_.CLK (19.788:19.788:19.788) (12.562:12.562:12.562))
(INTERCONNECT io_in[12] _2746_.CLK (19.788:19.788:19.788) (12.562:12.562:12.562))
(INTERCONNECT io_in[12] _2745_.CLK (19.790:19.790:19.790) (12.563:12.563:12.563))
(INTERCONNECT io_in[12] _2744_.CLK (19.792:19.792:19.792) (12.565:12.565:12.565))
(INTERCONNECT io_in[12] _2652_.CLK (19.793:19.793:19.793) (12.566:12.566:12.566))
(INTERCONNECT io_in[12] _2615_.CLK (19.785:19.785:19.785) (12.559:12.559:12.559))
(INTERCONNECT io_in[12] _2579_.CLK (19.776:19.776:19.776) (12.550:12.550:12.550))
(INTERCONNECT io_in[12] _2606_.CLK (19.777:19.777:19.777) (12.551:12.551:12.551))
(INTERCONNECT io_in[12] _2623_.CLK (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] _2586_.CLK (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] _2604_.CLK (19.781:19.781:19.781) (12.554:12.554:12.554))
(INTERCONNECT io_in[12] _2605_.CLK (19.781:19.781:19.781) (12.554:12.554:12.554))
(INTERCONNECT io_in[12] _2580_.CLK (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] _2602_.CLK (19.776:19.776:19.776) (12.550:12.550:12.550))
(INTERCONNECT io_in[12] _2632_.CLK (19.757:19.757:19.757) (12.531:12.531:12.531))
(INTERCONNECT io_in[12] _2589_.CLK (19.772:19.772:19.772) (12.546:12.546:12.546))
(INTERCONNECT io_in[12] _2598_.CLK (19.766:19.766:19.766) (12.540:12.540:12.540))
(INTERCONNECT io_in[12] _2599_.CLK (19.758:19.758:19.758) (12.532:12.532:12.532))
(INTERCONNECT io_in[12] _2600_.CLK (19.748:19.748:19.748) (12.522:12.522:12.522))
(INTERCONNECT io_in[12] _2573_.CLK (19.754:19.754:19.754) (12.528:12.528:12.528))
(INTERCONNECT io_in[12] _2601_.CLK (19.760:19.760:19.760) (12.534:12.534:12.534))
(INTERCONNECT io_in[12] _2597_.CLK (19.755:19.755:19.755) (12.529:12.529:12.529))
(INTERCONNECT io_in[12] _2616_.CLK (19.770:19.770:19.770) (12.544:12.544:12.544))
(INTERCONNECT io_in[12] _2574_.CLK (19.772:19.772:19.772) (12.546:12.546:12.546))
(INTERCONNECT io_in[12] _2588_.CLK (19.772:19.772:19.772) (12.546:12.546:12.546))
(INTERCONNECT io_in[12] _2613_.CLK (19.749:19.749:19.749) (12.523:12.523:12.523))
(INTERCONNECT io_in[12] _2596_.CLK (19.768:19.768:19.768) (12.542:12.542:12.542))
(INTERCONNECT io_in[12] _2575_.CLK (19.768:19.768:19.768) (12.542:12.542:12.542))
(INTERCONNECT io_in[12] _2621_.CLK (19.775:19.775:19.775) (12.549:12.549:12.549))
(INTERCONNECT io_in[12] _2622_.CLK (19.773:19.773:19.773) (12.547:12.547:12.547))
(INTERCONNECT io_in[12] _2584_.CLK (19.776:19.776:19.776) (12.549:12.549:12.549))
(INTERCONNECT io_in[12] _2582_.CLK (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] _2578_.CLK (19.775:19.775:19.775) (12.549:12.549:12.549))
(INTERCONNECT io_in[12] _2576_.CLK (19.769:19.769:19.769) (12.543:12.543:12.543))
(INTERCONNECT io_in[12] _2612_.CLK (19.771:19.771:19.771) (12.545:12.545:12.545))
(INTERCONNECT io_in[12] _2595_.CLK (19.770:19.770:19.770) (12.544:12.544:12.544))
(INTERCONNECT io_in[12] _2583_.CLK (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] _2577_.CLK (19.775:19.775:19.775) (12.549:12.549:12.549))
(INTERCONNECT io_in[12] _2581_.CLK (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] _2585_.CLK (19.776:19.776:19.776) (12.550:12.550:12.550))
(INTERCONNECT io_in[12] _2611_.CLK (19.776:19.776:19.776) (12.550:12.550:12.550))
(INTERCONNECT io_in[12] ANTENNA__2611__CLK.I (19.778:19.778:19.778) (12.551:12.551:12.551))
(INTERCONNECT io_in[12] ANTENNA__2585__CLK.I (19.776:19.776:19.776) (12.550:12.550:12.550))
(INTERCONNECT io_in[12] ANTENNA__2581__CLK.I (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] ANTENNA__2577__CLK.I (19.775:19.775:19.775) (12.549:12.549:12.549))
(INTERCONNECT io_in[12] ANTENNA__2583__CLK.I (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] ANTENNA__2595__CLK.I (19.749:19.749:19.749) (12.523:12.523:12.523))
(INTERCONNECT io_in[12] ANTENNA__2612__CLK.I (19.749:19.749:19.749) (12.523:12.523:12.523))
(INTERCONNECT io_in[12] ANTENNA__2576__CLK.I (19.769:19.769:19.769) (12.543:12.543:12.543))
(INTERCONNECT io_in[12] ANTENNA__2578__CLK.I (19.776:19.776:19.776) (12.550:12.550:12.550))
(INTERCONNECT io_in[12] ANTENNA__2582__CLK.I (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] ANTENNA__2584__CLK.I (19.775:19.775:19.775) (12.549:12.549:12.549))
(INTERCONNECT io_in[12] ANTENNA__2622__CLK.I (19.775:19.775:19.775) (12.549:12.549:12.549))
(INTERCONNECT io_in[12] ANTENNA__2621__CLK.I (19.775:19.775:19.775) (12.549:12.549:12.549))
(INTERCONNECT io_in[12] ANTENNA__2575__CLK.I (19.768:19.768:19.768) (12.542:12.542:12.542))
(INTERCONNECT io_in[12] ANTENNA__2596__CLK.I (19.749:19.749:19.749) (12.523:12.523:12.523))
(INTERCONNECT io_in[12] ANTENNA__2613__CLK.I (19.749:19.749:19.749) (12.523:12.523:12.523))
(INTERCONNECT io_in[12] ANTENNA__2588__CLK.I (19.772:19.772:19.772) (12.546:12.546:12.546))
(INTERCONNECT io_in[12] ANTENNA__2574__CLK.I (19.772:19.772:19.772) (12.546:12.546:12.546))
(INTERCONNECT io_in[12] ANTENNA__2616__CLK.I (19.770:19.770:19.770) (12.544:12.544:12.544))
(INTERCONNECT io_in[12] ANTENNA__2597__CLK.I (19.754:19.754:19.754) (12.528:12.528:12.528))
(INTERCONNECT io_in[12] ANTENNA__2601__CLK.I (19.749:19.749:19.749) (12.523:12.523:12.523))
(INTERCONNECT io_in[12] ANTENNA__2573__CLK.I (19.749:19.749:19.749) (12.523:12.523:12.523))
(INTERCONNECT io_in[12] ANTENNA__2600__CLK.I (19.749:19.749:19.749) (12.523:12.523:12.523))
(INTERCONNECT io_in[12] ANTENNA__2599__CLK.I (19.749:19.749:19.749) (12.523:12.523:12.523))
(INTERCONNECT io_in[12] ANTENNA__2598__CLK.I (19.761:19.761:19.761) (12.535:12.535:12.535))
(INTERCONNECT io_in[12] ANTENNA__2589__CLK.I (19.755:19.755:19.755) (12.529:12.529:12.529))
(INTERCONNECT io_in[12] ANTENNA__2632__CLK.I (19.757:19.757:19.757) (12.531:12.531:12.531))
(INTERCONNECT io_in[12] ANTENNA__2602__CLK.I (19.776:19.776:19.776) (12.550:12.550:12.550))
(INTERCONNECT io_in[12] ANTENNA__2580__CLK.I (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] ANTENNA__2605__CLK.I (19.781:19.781:19.781) (12.554:12.554:12.554))
(INTERCONNECT io_in[12] ANTENNA__2604__CLK.I (19.781:19.781:19.781) (12.554:12.554:12.554))
(INTERCONNECT io_in[12] ANTENNA__2586__CLK.I (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] ANTENNA__2623__CLK.I (19.781:19.781:19.781) (12.555:12.555:12.555))
(INTERCONNECT io_in[12] ANTENNA__2606__CLK.I (19.777:19.777:19.777) (12.551:12.551:12.551))
(INTERCONNECT io_in[12] ANTENNA__2579__CLK.I (19.776:19.776:19.776) (12.550:12.550:12.550))
(INTERCONNECT io_in[12] ANTENNA__2615__CLK.I (19.784:19.784:19.784) (12.557:12.557:12.557))
(INTERCONNECT io_in[12] ANTENNA__2652__CLK.I (19.788:19.788:19.788) (12.562:12.562:12.562))
(INTERCONNECT io_in[12] ANTENNA__2744__CLK.I (19.786:19.786:19.786) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] ANTENNA__2745__CLK.I (19.787:19.787:19.787) (12.561:12.561:12.561))
(INTERCONNECT io_in[12] ANTENNA__2746__CLK.I (19.786:19.786:19.786) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] ANTENNA__2752__CLK.I (19.787:19.787:19.787) (12.561:12.561:12.561))
(INTERCONNECT io_in[12] ANTENNA__2749__CLK.I (19.756:19.756:19.756) (12.529:12.529:12.529))
(INTERCONNECT io_in[12] ANTENNA__2751__CLK.I (19.793:19.793:19.793) (12.566:12.566:12.566))
(INTERCONNECT io_in[12] ANTENNA__2657__CLK.I (19.755:19.755:19.755) (12.529:12.529:12.529))
(INTERCONNECT io_in[12] ANTENNA__2626__CLK.I (19.735:19.735:19.735) (12.509:12.509:12.509))
(INTERCONNECT io_in[12] ANTENNA__2628__CLK.I (19.736:19.736:19.736) (12.510:12.510:12.510))
(INTERCONNECT io_in[12] ANTENNA__2629__CLK.I (19.740:19.740:19.740) (12.514:12.514:12.514))
(INTERCONNECT io_in[12] ANTENNA__2633__CLK.I (19.744:19.744:19.744) (12.518:12.518:12.518))
(INTERCONNECT io_in[12] ANTENNA__2630__CLK.I (19.743:19.743:19.743) (12.517:12.517:12.517))
(INTERCONNECT io_in[12] ANTENNA__2631__CLK.I (19.744:19.744:19.744) (12.518:12.518:12.518))
(INTERCONNECT io_in[12] ANTENNA__2725__CLK.I (19.736:19.736:19.736) (12.510:12.510:12.510))
(INTERCONNECT io_in[12] ANTENNA_mod\.u_cpu\.rf_ram\.RAM0_CLK.I (19.732:19.732:19.732) (12.507:12.507:12.507))
(INTERCONNECT io_in[12] ANTENNA__2624__CLK.I (19.705:19.705:19.705) (12.479:12.479:12.479))
(INTERCONNECT io_in[12] ANTENNA__2587__CLK.I (19.733:19.733:19.733) (12.507:12.507:12.507))
(INTERCONNECT io_in[12] ANTENNA__2793__CLK.I (19.689:19.689:19.689) (12.463:12.463:12.463))
(INTERCONNECT io_in[12] ANTENNA__2795__CLK.I (19.678:19.678:19.678) (12.453:12.453:12.453))
(INTERCONNECT io_in[12] ANTENNA__2798__CLK.I (19.691:19.691:19.691) (12.465:12.465:12.465))
(INTERCONNECT io_in[12] ANTENNA__2805__CLK.I (19.725:19.725:19.725) (12.499:12.499:12.499))
(INTERCONNECT io_in[12] ANTENNA__2603__CLK.I (19.732:19.732:19.732) (12.506:12.506:12.506))
(INTERCONNECT io_in[12] ANTENNA__2797__CLK.I (19.732:19.732:19.732) (12.506:12.506:12.506))
(INTERCONNECT io_in[12] ANTENNA__2627__CLK.I (19.733:19.733:19.733) (12.508:12.508:12.508))
(INTERCONNECT io_in[12] ANTENNA__2726__CLK.I (19.733:19.733:19.733) (12.508:12.508:12.508))
(INTERCONNECT io_in[12] ANTENNA__2625__CLK.I (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] ANTENNA__2651__CLK.I (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] ANTENNA__2694__CLK.I (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] ANTENNA__2759__CLK.I (19.794:19.794:19.794) (12.568:12.568:12.568))
(INTERCONNECT io_in[12] ANTENNA__2796__CLK.I (19.661:19.661:19.661) (12.436:12.436:12.436))
(INTERCONNECT io_in[12] ANTENNA__2754__CLK.I (19.756:19.756:19.756) (12.530:12.530:12.530))
(INTERCONNECT io_in[12] ANTENNA__2737__CLK.I (19.798:19.798:19.798) (12.571:12.571:12.571))
(INTERCONNECT io_in[12] ANTENNA__2755__CLK.I (19.756:19.756:19.756) (12.530:12.530:12.530))
(INTERCONNECT io_in[12] ANTENNA__2753__CLK.I (19.756:19.756:19.756) (12.530:12.530:12.530))
(INTERCONNECT io_in[12] ANTENNA__2757__CLK.I (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] ANTENNA__2691__CLK.I (19.665:19.665:19.665) (12.440:12.440:12.440))
(INTERCONNECT io_in[12] ANTENNA__2637__CLK.I (19.505:19.505:19.505) (12.281:12.281:12.281))
(INTERCONNECT io_in[12] ANTENNA__2729__CLK.I (19.793:19.793:19.793) (12.566:12.566:12.566))
(INTERCONNECT io_in[12] ANTENNA__2732__CLK.I (19.802:19.802:19.802) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] ANTENNA__2738__CLK.I (19.800:19.800:19.800) (12.573:12.573:12.573))
(INTERCONNECT io_in[12] ANTENNA__2728__CLK.I (19.793:19.793:19.793) (12.566:12.566:12.566))
(INTERCONNECT io_in[12] ANTENNA__2756__CLK.I (19.800:19.800:19.800) (12.573:12.573:12.573))
(INTERCONNECT io_in[12] ANTENNA__2727__CLK.I (19.508:19.508:19.508) (12.284:12.284:12.284))
(INTERCONNECT io_in[12] ANTENNA__2739__CLK.I (19.508:19.508:19.508) (12.284:12.284:12.284))
(INTERCONNECT io_in[12] ANTENNA__2740__CLK.I (19.508:19.508:19.508) (12.284:12.284:12.284))
(INTERCONNECT io_in[12] ANTENNA__2741__CLK.I (19.508:19.508:19.508) (12.283:12.283:12.283))
(INTERCONNECT io_in[12] ANTENNA__2743__CLK.I (19.508:19.508:19.508) (12.284:12.284:12.284))
(INTERCONNECT io_in[12] ANTENNA__2742__CLK.I (19.508:19.508:19.508) (12.284:12.284:12.284))
(INTERCONNECT io_in[12] ANTENNA__2765__CLK.I (19.508:19.508:19.508) (12.284:12.284:12.284))
(INTERCONNECT io_in[12] ANTENNA__2766__CLK.I (19.509:19.509:19.509) (12.285:12.285:12.285))
(INTERCONNECT io_in[12] ANTENNA__2760__CLK.I (19.800:19.800:19.800) (12.573:12.573:12.573))
(INTERCONNECT io_in[12] ANTENNA__2641__CLK.I (19.498:19.498:19.498) (12.274:12.274:12.274))
(INTERCONNECT io_in[12] ANTENNA__2758__CLK.I (19.803:19.803:19.803) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] ANTENNA__2736__CLK.I (19.786:19.786:19.786) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] ANTENNA__2654__CLK.I (19.803:19.803:19.803) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] ANTENNA__2656__CLK.I (19.802:19.802:19.802) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] ANTENNA__2734__CLK.I (19.787:19.787:19.787) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] ANTENNA__2748__CLK.I (19.787:19.787:19.787) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] ANTENNA__2735__CLK.I (19.787:19.787:19.787) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] ANTENNA__2730__CLK.I (19.800:19.800:19.800) (12.574:12.574:12.574))
(INTERCONNECT io_in[12] ANTENNA__2731__CLK.I (19.801:19.801:19.801) (12.574:12.574:12.574))
(INTERCONNECT io_in[12] ANTENNA__2653__CLK.I (19.802:19.802:19.802) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] ANTENNA__2655__CLK.I (19.803:19.803:19.803) (12.576:12.576:12.576))
(INTERCONNECT io_in[12] ANTENNA__2733__CLK.I (19.787:19.787:19.787) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] ANTENNA__2747__CLK.I (19.787:19.787:19.787) (12.560:12.560:12.560))
(INTERCONNECT io_in[12] ANTENNA__2643__CLK.I (19.498:19.498:19.498) (12.274:12.274:12.274))
(INTERCONNECT io_in[12] ANTENNA__2639__CLK.I (19.498:19.498:19.498) (12.274:12.274:12.274))
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(IOPATH A3 ZN (1.273:1.273:1.273) (1.164:1.164:1.164))
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(IOPATH I ZN (1.939:1.939:1.939) (1.261:1.268:1.275))
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(IOPATH I ZN (0.426:0.426:0.426) (0.004:0.002:-0.001))
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(IOPATH A2 Z (0.806:0.806:0.806) (0.900:0.900:0.900))
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(IOPATH A1 ZN (0.931:0.931:0.931) (0.929:0.929:0.929))
(IOPATH A2 ZN (1.092:1.122:1.153) (0.982:0.982:0.982))
(IOPATH A3 ZN (0.955:0.972:0.990) (0.820:0.820:0.821))
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(COND A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1
(IOPATH C ZN (0.695:0.721:0.747) (0.283:0.283:0.282)))
(COND A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0
(IOPATH C ZN (0.592:0.613:0.634) (0.321:0.321:0.321)))
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)
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(CELL
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(ABSOLUTE
(IOPATH A1 Z (0.119:0.119:0.119) (1.165:1.165:1.165))
(IOPATH A2 Z (0.299:0.310:0.321) (0.631:0.665:0.699))
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(IOPATH C ZN (0.264:0.266:0.268) (0.191:0.192:0.192)))
(COND A1===1'b0 && A2===1'b1
(IOPATH C ZN (0.274:0.276:0.278) (0.226:0.227:0.227)))
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(ABSOLUTE
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(IOPATH A1 ZN (1.321:1.345:1.369) (-0.087:-0.166:-0.245)))
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(IOPATH A1 ZN (1.076:1.097:1.117) (-0.127:-0.205:-0.282)))
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(IOPATH A1 ZN (1.133:1.155:1.176) (-0.081:-0.153:-0.225)))
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(CELL
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(CELL
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(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (-0.025:-0.025:-0.025))
(HOLD (negedge D) (posedge CLK) (0.059:0.059:0.059))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2610_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.543:1.543:1.543) (1.180:1.180:1.180))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.389:0.389:0.389))
(SETUP (negedge D) (posedge CLK) (0.168:0.168:0.168))
(HOLD (posedge D) (posedge CLK) (-0.118:-0.118:-0.118))
(HOLD (negedge D) (posedge CLK) (0.063:0.063:0.063))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2611_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.673:1.673:1.673) (1.273:1.273:1.273))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.394:0.394:0.394))
(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (0.009:0.009:0.009))
(HOLD (negedge D) (posedge CLK) (0.056:0.056:0.056))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2612_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.435:1.435:1.435) (1.109:1.109:1.109))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.389:0.389:0.389))
(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (0.009:0.009:0.009))
(HOLD (negedge D) (posedge CLK) (0.056:0.056:0.056))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2613_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.446:1.446:1.446) (1.117:1.117:1.117))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.395:0.383:0.371))
(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.172))
(HOLD (posedge D) (posedge CLK) (0.010:0.005:0.001))
(HOLD (negedge D) (posedge CLK) (0.059:0.060:0.061))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2614_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.489:1.489:1.489) (1.144:1.144:1.144))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.397:0.385:0.374))
(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.172))
(HOLD (posedge D) (posedge CLK) (0.010:-0.005:-0.020))
(HOLD (negedge D) (posedge CLK) (0.055:0.058:0.061))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2615_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.552:1.552:1.552) (1.187:1.187:1.187))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.394:0.391:0.389))
(SETUP (negedge D) (posedge CLK) (0.126:0.150:0.173))
(HOLD (posedge D) (posedge CLK) (0.010:0.009:0.009))
(HOLD (negedge D) (posedge CLK) (0.066:0.061:0.057))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2616_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.377:1.377:1.377) (1.066:1.066:1.066))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.399:0.399:0.399))
(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (0.010:0.010:0.010))
(HOLD (negedge D) (posedge CLK) (0.056:0.056:0.056))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2617_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.395:1.395:1.395) (1.081:1.081:1.081))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.386:0.386:0.386))
(SETUP (negedge D) (posedge CLK) (0.170:0.170:0.170))
(HOLD (posedge D) (posedge CLK) (-0.099:-0.099:-0.099))
(HOLD (negedge D) (posedge CLK) (0.063:0.063:0.063))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2618_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.384:1.384:1.384) (1.072:1.072:1.072))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.413:0.413:0.413))
(SETUP (negedge D) (posedge CLK) (0.160:0.160:0.160))
(HOLD (posedge D) (posedge CLK) (-0.068:-0.068:-0.068))
(HOLD (negedge D) (posedge CLK) (0.062:0.062:0.062))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2619_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.382:1.382:1.382) (1.070:1.070:1.070))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.404:0.404:0.404))
(SETUP (negedge D) (posedge CLK) (0.160:0.160:0.160))
(HOLD (posedge D) (posedge CLK) (-0.086:-0.086:-0.086))
(HOLD (negedge D) (posedge CLK) (0.064:0.064:0.064))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2620_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.387:1.387:1.387) (1.074:1.074:1.074))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.373:0.373:0.373))
(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (-0.012:-0.012:-0.012))
(HOLD (negedge D) (posedge CLK) (0.059:0.059:0.059))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2621_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.389:1.389:1.389) (1.076:1.076:1.076))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.374:0.374:0.374))
(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (0.006:0.006:0.006))
(HOLD (negedge D) (posedge CLK) (0.058:0.058:0.058))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2622_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.380:1.380:1.380) (1.069:1.069:1.069))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.379:0.378:0.378))
(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (0.007:0.007:0.007))
(HOLD (negedge D) (posedge CLK) (0.057:0.057:0.057))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2623_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.383:1.383:1.383) (1.071:1.071:1.071))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.401:0.401:0.401))
(SETUP (negedge D) (posedge CLK) (0.174:0.174:0.174))
(HOLD (posedge D) (posedge CLK) (0.011:0.011:0.011))
(HOLD (negedge D) (posedge CLK) (0.055:0.055:0.055))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2624_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.832:1.832:1.832) (1.376:1.376:1.376))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.394:0.384:0.373))
(SETUP (negedge D) (posedge CLK) (0.173:0.169:0.166))
(HOLD (posedge D) (posedge CLK) (0.010:-0.003:-0.015))
(HOLD (negedge D) (posedge CLK) (0.056:0.060:0.064))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2625_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.704:1.704:1.704) (1.294:1.294:1.294))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.408:0.392:0.377))
(SETUP (negedge D) (posedge CLK) (0.118:0.142:0.166))
(HOLD (posedge D) (posedge CLK) (0.012:-0.016:-0.045))
(HOLD (negedge D) (posedge CLK) (0.068:0.066:0.064))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2626_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.571:1.571:1.571) (1.200:1.200:1.200))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.396:0.405:0.414))
(SETUP (negedge D) (posedge CLK) (0.109:0.132:0.155))
(HOLD (posedge D) (posedge CLK) (0.021:0.017:0.013))
(HOLD (negedge D) (posedge CLK) (0.069:0.064:0.059))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2627_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.433:1.433:1.433) (1.108:1.108:1.108))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.395:0.383:0.371))
(SETUP (negedge D) (posedge CLK) (0.169:0.170:0.172))
(HOLD (posedge D) (posedge CLK) (0.010:0.008:0.005))
(HOLD (negedge D) (posedge CLK) (0.056:0.059:0.063))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2628_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.466:1.466:1.466) (1.129:1.129:1.129))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.394:0.383:0.371))
(SETUP (negedge D) (posedge CLK) (0.152:0.162:0.173))
(HOLD (posedge D) (posedge CLK) (0.010:0.003:-0.003))
(HOLD (negedge D) (posedge CLK) (0.060:0.060:0.060))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2629_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.440:1.440:1.440) (1.113:1.113:1.113))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.392:0.392:0.392))
(SETUP (negedge D) (posedge CLK) (0.086:0.086:0.086))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2630_)
(DELAY
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(IOPATH CLK Q (1.476:1.476:1.476) (1.135:1.135:1.135))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.394:0.394:0.394))
(SETUP (negedge D) (posedge CLK) (0.088:0.088:0.089))
(HOLD (posedge D) (posedge CLK) (0.022:0.022:0.022))
(HOLD (negedge D) (posedge CLK) (0.074:0.074:0.074))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2631_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.393:1.393:1.393) (1.079:1.079:1.079))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.392:0.387:0.382))
(SETUP (negedge D) (posedge CLK) (0.174:0.171:0.169))
(HOLD (posedge D) (posedge CLK) (0.009:-0.033:-0.076))
(HOLD (negedge D) (posedge CLK) (0.055:0.059:0.063))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2632_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.385:1.385:1.385) (1.072:1.072:1.072))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.395:0.388:0.381))
(SETUP (negedge D) (posedge CLK) (0.173:0.171:0.170))
(HOLD (posedge D) (posedge CLK) (0.010:-0.030:-0.070))
(HOLD (negedge D) (posedge CLK) (0.055:0.059:0.063))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2633_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.443:1.443:1.443) (1.115:1.115:1.115))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.399:0.393:0.386))
(SETUP (negedge D) (posedge CLK) (0.169:0.167:0.164))
(HOLD (posedge D) (posedge CLK) (0.011:-0.047:-0.105))
(HOLD (negedge D) (posedge CLK) (0.056:0.060:0.064))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2634_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.586:1.586:1.586) (1.211:1.211:1.211))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.408:0.409:0.409))
(SETUP (negedge D) (posedge CLK) (0.111:0.112:0.113))
(HOLD (posedge D) (posedge CLK) (0.016:0.016:0.016))
(HOLD (negedge D) (posedge CLK) (0.069:0.069:0.069))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2635_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.649:1.649:1.649) (1.256:1.256:1.256))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.388:0.388:0.388))
(SETUP (negedge D) (posedge CLK) (0.079:0.080:0.081))
(HOLD (posedge D) (posedge CLK) (0.025:0.024:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2636_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.518:1.518:1.518) (1.162:1.162:1.162))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.389:0.389:0.390))
(SETUP (negedge D) (posedge CLK) (0.081:0.082:0.083))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.075:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(DELAY
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(SETUP (negedge D) (posedge CLK) (0.081:0.082:0.083))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2638_)
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(SETUP (negedge D) (posedge CLK) (0.112:0.113:0.113))
(HOLD (posedge D) (posedge CLK) (0.016:0.016:0.016))
(HOLD (negedge D) (posedge CLK) (0.069:0.069:0.069))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2639_)
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(SETUP (negedge D) (posedge CLK) (0.136:0.137:0.137))
(HOLD (posedge D) (posedge CLK) (0.013:0.013:0.013))
(HOLD (negedge D) (posedge CLK) (0.064:0.063:0.063))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2640_)
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(SETUP (negedge D) (posedge CLK) (0.087:0.089:0.090))
(HOLD (posedge D) (posedge CLK) (0.022:0.022:0.022))
(HOLD (negedge D) (posedge CLK) (0.074:0.074:0.074))
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(INSTANCE _2641_)
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(SETUP (negedge D) (posedge CLK) (0.095:0.096:0.097))
(HOLD (posedge D) (posedge CLK) (0.020:0.020:0.020))
(HOLD (negedge D) (posedge CLK) (0.073:0.072:0.072))
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(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2642_)
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(SETUP (negedge D) (posedge CLK) (0.105:0.106:0.107))
(HOLD (posedge D) (posedge CLK) (0.017:0.017:0.017))
(HOLD (negedge D) (posedge CLK) (0.070:0.070:0.070))
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(INSTANCE _2643_)
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(SETUP (negedge D) (posedge CLK) (0.083:0.084:0.085))
(HOLD (posedge D) (posedge CLK) (0.024:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
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(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2644_)
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(SETUP (negedge D) (posedge CLK) (0.101:0.102:0.103))
(HOLD (posedge D) (posedge CLK) (0.018:0.018:0.018))
(HOLD (negedge D) (posedge CLK) (0.071:0.071:0.071))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2645_)
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(SETUP (negedge D) (posedge CLK) (0.076:0.077:0.078))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2646_)
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(SETUP (negedge D) (posedge CLK) (0.076:0.077:0.078))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.077:0.077:0.076))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2647_)
(DELAY
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(SETUP (negedge D) (posedge CLK) (0.082:0.083:0.084))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.023))
(HOLD (negedge D) (posedge CLK) (0.076:0.075:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2648_)
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(SETUP (negedge D) (posedge CLK) (0.103:0.104:0.105))
(HOLD (posedge D) (posedge CLK) (0.018:0.018:0.018))
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(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2649_)
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(SETUP (negedge D) (posedge CLK) (0.077:0.078:0.079))
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(INSTANCE _2650_)
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(SETUP (negedge D) (posedge CLK) (0.173:0.169:0.165))
(HOLD (posedge D) (posedge CLK) (0.010:-0.004:-0.018))
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(INSTANCE _2651_)
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(TIMINGCHECK
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(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.172))
(HOLD (posedge D) (posedge CLK) (0.011:-0.007:-0.024))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2652_)
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(SETUP (negedge D) (posedge CLK) (0.173:0.166:0.159))
(HOLD (posedge D) (posedge CLK) (0.011:-0.037:-0.084))
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(INSTANCE _2653_)
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(TIMINGCHECK
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(SETUP (negedge D) (posedge CLK) (0.173:0.165:0.157))
(HOLD (posedge D) (posedge CLK) (0.007:-0.035:-0.077))
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(INSTANCE _2654_)
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(TIMINGCHECK
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(SETUP (negedge D) (posedge CLK) (0.173:0.168:0.164))
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(INSTANCE _2655_)
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(TIMINGCHECK
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(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.172))
(HOLD (posedge D) (posedge CLK) (0.009:-0.049:-0.107))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(CELL
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(INSTANCE _2656_)
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(SETUP (negedge D) (posedge CLK) (0.173:0.165:0.158))
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(CELL
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(INSTANCE _2657_)
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(SETUP (negedge D) (posedge CLK) (0.147:0.154:0.160))
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(INSTANCE _2658_)
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(SETUP (negedge D) (posedge CLK) (0.117:0.145:0.173))
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(INSTANCE _2659_)
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(INSTANCE _2661_)
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(SETUP (negedge D) (posedge CLK) (0.093:0.133:0.173))
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(INSTANCE _2662_)
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(SETUP (negedge D) (posedge CLK) (0.076:0.125:0.173))
(HOLD (posedge D) (posedge CLK) (0.021:0.016:0.010))
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(CELL
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(SETUP (negedge D) (posedge CLK) (0.107:0.140:0.173))
(HOLD (posedge D) (posedge CLK) (0.013:0.012:0.010))
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(CELL
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(SETUP (negedge D) (posedge CLK) (0.094:0.133:0.173))
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(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (0.009:-0.011:-0.030))
(HOLD (negedge D) (posedge CLK) (0.058:0.059:0.061))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2693_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.364:1.364:1.364) (1.055:1.055:1.055))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.401:0.386:0.371))
(SETUP (negedge D) (posedge CLK) (0.129:0.150:0.172))
(HOLD (posedge D) (posedge CLK) (0.011:0.005:-0.000))
(HOLD (negedge D) (posedge CLK) (0.065:0.064:0.063))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2694_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.458:1.458:1.458) (1.124:1.124:1.124))
)
)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.392:0.385:0.378))
(SETUP (negedge D) (posedge CLK) (0.165:0.166:0.168))
(HOLD (posedge D) (posedge CLK) (0.009:-0.018:-0.046))
(HOLD (negedge D) (posedge CLK) (0.057:0.060:0.063))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2695_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.647:1.647:1.647) (1.256:1.256:1.256))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.391:0.392:0.392))
(SETUP (negedge D) (posedge CLK) (0.085:0.086:0.086))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2696_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.510:1.510:1.510) (1.157:1.157:1.157))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.389:0.389:0.389))
(SETUP (negedge D) (posedge CLK) (0.081:0.082:0.082))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2697_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.500:1.500:1.500) (1.151:1.151:1.151))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.386:0.387:0.387))
(SETUP (negedge D) (posedge CLK) (0.077:0.078:0.078))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.077:0.077:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2698_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.536:1.536:1.536) (1.175:1.175:1.175))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.387:0.387:0.387))
(SETUP (negedge D) (posedge CLK) (0.078:0.078:0.079))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.077:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2699_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.540:1.540:1.540) (1.178:1.178:1.178))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.400:0.400:0.400))
(SETUP (negedge D) (posedge CLK) (0.098:0.098:0.099))
(HOLD (posedge D) (posedge CLK) (0.020:0.020:0.019))
(HOLD (negedge D) (posedge CLK) (0.072:0.072:0.072))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2700_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.518:1.518:1.518) (1.162:1.162:1.162))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.387:0.387:0.388))
(SETUP (negedge D) (posedge CLK) (0.079:0.079:0.080))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2701_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.516:1.516:1.516) (1.161:1.161:1.161))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.390:0.391:0.391))
(SETUP (negedge D) (posedge CLK) (0.084:0.084:0.085))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2702_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.524:1.524:1.524) (1.166:1.166:1.166))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.388:0.388:0.388))
(SETUP (negedge D) (posedge CLK) (0.080:0.080:0.081))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2703_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.500:1.500:1.500) (1.151:1.151:1.151))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.387:0.388:0.388))
(SETUP (negedge D) (posedge CLK) (0.079:0.079:0.080))
(HOLD (posedge D) (posedge CLK) (0.025:0.024:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2704_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.615:1.615:1.615) (1.232:1.232:1.232))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.387:0.388:0.388))
(SETUP (negedge D) (posedge CLK) (0.079:0.079:0.080))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2705_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.505:1.505:1.505) (1.154:1.154:1.154))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.396:0.396:0.397))
(SETUP (negedge D) (posedge CLK) (0.092:0.093:0.094))
(HOLD (posedge D) (posedge CLK) (0.021:0.021:0.021))
(HOLD (negedge D) (posedge CLK) (0.073:0.073:0.073))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2706_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.533:1.533:1.533) (1.172:1.172:1.172))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.387:0.387:0.387))
(SETUP (negedge D) (posedge CLK) (0.078:0.079:0.079))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2707_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.528:1.528:1.528) (1.169:1.169:1.169))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.396:0.396:0.397))
(SETUP (negedge D) (posedge CLK) (0.092:0.093:0.094))
(HOLD (posedge D) (posedge CLK) (0.021:0.021:0.021))
(HOLD (negedge D) (posedge CLK) (0.073:0.073:0.073))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2708_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.526:1.526:1.526) (1.168:1.168:1.168))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.388:0.388:0.388))
(SETUP (negedge D) (posedge CLK) (0.079:0.080:0.081))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2709_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.519:1.519:1.519) (1.163:1.163:1.163))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.395:0.395:0.395))
(SETUP (negedge D) (posedge CLK) (0.090:0.091:0.091))
(HOLD (posedge D) (posedge CLK) (0.022:0.021:0.021))
(HOLD (negedge D) (posedge CLK) (0.074:0.074:0.074))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2710_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.532:1.532:1.532) (1.172:1.172:1.172))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.394:0.394:0.395))
(SETUP (negedge D) (posedge CLK) (0.089:0.090:0.091))
(HOLD (posedge D) (posedge CLK) (0.022:0.022:0.022))
(HOLD (negedge D) (posedge CLK) (0.074:0.074:0.074))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2711_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.532:1.532:1.532) (1.172:1.172:1.172))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.384:0.385:0.385))
(SETUP (negedge D) (posedge CLK) (0.074:0.075:0.076))
(HOLD (posedge D) (posedge CLK) (0.026:0.026:0.026))
(HOLD (negedge D) (posedge CLK) (0.077:0.077:0.077))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2712_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.522:1.522:1.522) (1.165:1.165:1.165))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.391:0.391:0.391))
(SETUP (negedge D) (posedge CLK) (0.084:0.085:0.085))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2713_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.528:1.528:1.528) (1.169:1.169:1.169))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.387:0.387:0.387))
(SETUP (negedge D) (posedge CLK) (0.078:0.078:0.079))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.077:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2714_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.535:1.535:1.535) (1.174:1.174:1.174))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.384:0.385:0.385))
(SETUP (negedge D) (posedge CLK) (0.074:0.075:0.076))
(HOLD (posedge D) (posedge CLK) (0.026:0.026:0.026))
(HOLD (negedge D) (posedge CLK) (0.077:0.077:0.077))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2715_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.539:1.539:1.539) (1.177:1.177:1.177))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.386:0.386:0.386))
(SETUP (negedge D) (posedge CLK) (0.076:0.077:0.078))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.077:0.077:0.077))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2716_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.530:1.530:1.530) (1.171:1.171:1.171))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.392:0.392:0.392))
(SETUP (negedge D) (posedge CLK) (0.086:0.086:0.087))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2717_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.616:1.616:1.616) (1.233:1.233:1.233))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.387:0.387:0.387))
(SETUP (negedge D) (posedge CLK) (0.078:0.079:0.079))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.077:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2718_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.635:1.635:1.635) (1.247:1.247:1.247))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.403:0.403:0.404))
(SETUP (negedge D) (posedge CLK) (0.103:0.104:0.105))
(HOLD (posedge D) (posedge CLK) (0.018:0.018:0.018))
(HOLD (negedge D) (posedge CLK) (0.071:0.071:0.071))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2719_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.515:1.515:1.515) (1.160:1.160:1.160))
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)
(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.387:0.387:0.387))
(SETUP (negedge D) (posedge CLK) (0.078:0.079:0.080))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffq_1")
(INSTANCE _2720_)
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(INSTANCE _2803_)
(DELAY
(ABSOLUTE
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(SETUP (negedge D) (posedge CLK) (0.173:0.172:0.172))
(HOLD (posedge D) (posedge CLK) (0.009:0.007:0.005))
(HOLD (negedge D) (posedge CLK) (0.057:0.060:0.063))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2804_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.980:1.980:1.980) (1.475:1.475:1.475))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.386:0.381:0.376))
(SETUP (negedge D) (posedge CLK) (0.173:0.168:0.163))
(HOLD (posedge D) (posedge CLK) (0.008:-0.012:-0.033))
(HOLD (negedge D) (posedge CLK) (0.057:0.060:0.064))
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(INSTANCE _2805_)
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.452:1.452:1.452) (1.120:1.120:1.120))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.381:0.388:0.395))
(SETUP (negedge D) (posedge CLK) (0.167:0.192:0.217))
(HOLD (posedge D) (posedge CLK) (-0.071:-0.087:-0.104))
(HOLD (negedge D) (posedge CLK) (0.063:0.050:0.037))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__buf_1")
(INSTANCE _3129_)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.857:0.857:0.857) (0.661:0.661:0.661))
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)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__buf_1")
(INSTANCE _3130_)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.858:0.858:0.858) (0.663:0.663:0.663))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_ip_sram__sram256x8m8wm1")
(INSTANCE mod\.u_cpu\.rf_ram\.RAM0)
(DELAY
(ABSOLUTE
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[0] (21.758:21.758:21.758) (22.406:22.406:22.406)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[1] (21.775:21.775:21.775) (22.430:22.430:22.430)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[2] (21.744:21.744:21.744) (22.384:22.384:22.384)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[3] (21.754:21.754:21.754) (22.400:22.400:22.400)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[4] (21.759:21.759:21.759) (22.407:22.407:22.407)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[5] (21.755:21.755:21.755) (22.401:22.401:22.401)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[6] (21.750:21.750:21.750) (22.394:22.394:22.394)))
(COND CEN== 1'b0 && GWEN== 1'b1
(IOPATH CLK Q[7] (21.746:21.746:21.746) (22.388:22.388:22.388)))
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(TIMINGCHECK
(HOLD (posedge D[0]) (posedge CLK) (4.661:4.661:4.661))
(HOLD (negedge D[0]) (posedge CLK) (5.887:5.887:5.887))
(HOLD (posedge D[1]) (posedge CLK) (4.617:4.617:4.617))
(HOLD (negedge D[1]) (posedge CLK) (5.834:5.834:5.833))
(HOLD (posedge D[2]) (posedge CLK) (4.638:4.638:4.638))
(HOLD (negedge D[2]) (posedge CLK) (5.858:5.858:5.858))
(HOLD (posedge D[3]) (posedge CLK) (4.704:4.704:4.704))
(HOLD (negedge D[3]) (posedge CLK) (5.939:5.939:5.939))
(HOLD (posedge D[4]) (posedge CLK) (4.646:4.646:4.646))
(HOLD (negedge D[4]) (posedge CLK) (5.869:5.869:5.869))
(HOLD (posedge D[5]) (posedge CLK) (4.658:4.658:4.658))
(HOLD (negedge D[5]) (posedge CLK) (5.883:5.884:5.884))
(HOLD (posedge D[6]) (posedge CLK) (4.643:4.643:4.643))
(HOLD (negedge D[6]) (posedge CLK) (5.864:5.864:5.864))
(HOLD (posedge D[7]) (posedge CLK) (4.577:4.540:4.503))
(HOLD (negedge D[7]) (posedge CLK) (5.778:5.641:5.504))
(SETUP (posedge D[0]) (posedge CLK) (-1.731:-1.731:-1.731))
(SETUP (negedge D[0]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (posedge D[1]) (posedge CLK) (-1.701:-1.701:-1.701))
(SETUP (negedge D[1]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (posedge D[2]) (posedge CLK) (-1.715:-1.715:-1.715))
(SETUP (negedge D[2]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (posedge D[3]) (posedge CLK) (-1.762:-1.762:-1.762))
(SETUP (negedge D[3]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (posedge D[4]) (posedge CLK) (-1.721:-1.721:-1.721))
(SETUP (negedge D[4]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (posedge D[5]) (posedge CLK) (-1.729:-1.729:-1.729))
(SETUP (negedge D[5]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (posedge D[6]) (posedge CLK) (-1.718:-1.718:-1.718))
(SETUP (negedge D[6]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (posedge D[7]) (posedge CLK) (-1.673:-1.678:-1.684))
(SETUP (negedge D[7]) (posedge CLK) (-0.558:-1.938:-3.318))
(HOLD (posedge A[0]) (posedge CLK) (7.595:7.595:7.594))
(HOLD (negedge A[0]) (posedge CLK) (7.905:7.905:7.905))
(HOLD (posedge A[1]) (posedge CLK) (7.487:7.487:7.487))
(HOLD (negedge A[1]) (posedge CLK) (7.853:7.854:7.854))
(HOLD (posedge A[2]) (posedge CLK) (7.656:7.544:7.431))
(HOLD (negedge A[2]) (posedge CLK) (7.937:7.890:7.842))
(HOLD (posedge A[3]) (posedge CLK) (7.536:7.387:7.239))
(HOLD (negedge A[3]) (posedge CLK) (7.872:7.825:7.777))
(HOLD (posedge A[4]) (posedge CLK) (7.229:7.194:7.159))
(HOLD (negedge A[4]) (posedge CLK) (7.868:7.817:7.767))
(HOLD (posedge A[5]) (posedge CLK) (7.502:7.342:7.182))
(HOLD (negedge A[5]) (posedge CLK) (7.855:7.806:7.758))
(HOLD (posedge A[6]) (posedge CLK) (7.181:7.152:7.122))
(HOLD (negedge A[6]) (posedge CLK) (7.854:7.802:7.750))
(HOLD (posedge A[7]) (posedge CLK) (7.567:7.462:7.356))
(HOLD (negedge A[7]) (posedge CLK) (7.876:7.780:7.685))
(SETUP (posedge A[0]) (posedge CLK) (-1.960:-1.960:-1.959))
(SETUP (negedge A[0]) (posedge CLK) (-1.454:-1.454:-1.454))
(SETUP (posedge A[1]) (posedge CLK) (-1.802:-1.802:-1.802))
(SETUP (negedge A[1]) (posedge CLK) (-1.431:-1.431:-1.431))
(SETUP (posedge A[2]) (posedge CLK) (-2.058:-1.899:-1.740))
(SETUP (negedge A[2]) (posedge CLK) (-1.587:-1.510:-1.434))
(SETUP (posedge A[3]) (posedge CLK) (-1.867:-1.698:-1.530))
(SETUP (negedge A[3]) (posedge CLK) (-1.426:-1.439:-1.452))
(SETUP (posedge A[4]) (posedge CLK) (-1.519:-1.478:-1.436))
(SETUP (negedge A[4]) (posedge CLK) (-1.427:-1.441:-1.455))
(SETUP (posedge A[5]) (posedge CLK) (-1.818:-1.643:-1.468))
(SETUP (negedge A[5]) (posedge CLK) (-1.430:-1.444:-1.457))
(SETUP (posedge A[6]) (posedge CLK) (-1.467:-1.425:-1.382))
(SETUP (negedge A[6]) (posedge CLK) (-1.431:-1.445:-1.459))
(SETUP (posedge A[7]) (posedge CLK) (-1.916:-1.787:-1.659))
(SETUP (negedge A[7]) (posedge CLK) (-1.425:-1.430:-1.435))
(HOLD (posedge WEN[0]) (posedge CLK) (5.597:5.597:5.597))
(HOLD (negedge WEN[0]) (posedge CLK) (4.177:4.177:4.178))
(HOLD (posedge WEN[1]) (posedge CLK) (5.597:5.597:5.597))
(HOLD (negedge WEN[1]) (posedge CLK) (4.177:4.177:4.178))
(HOLD (posedge WEN[2]) (posedge CLK) (5.597:5.597:5.597))
(HOLD (negedge WEN[2]) (posedge CLK) (4.177:4.177:4.178))
(HOLD (posedge WEN[3]) (posedge CLK) (5.597:5.597:5.597))
(HOLD (negedge WEN[3]) (posedge CLK) (4.177:4.177:4.178))
(HOLD (posedge WEN[4]) (posedge CLK) (5.597:5.597:5.597))
(HOLD (negedge WEN[4]) (posedge CLK) (4.177:4.177:4.178))
(HOLD (posedge WEN[5]) (posedge CLK) (5.597:5.597:5.597))
(HOLD (negedge WEN[5]) (posedge CLK) (4.177:4.177:4.178))
(HOLD (posedge WEN[6]) (posedge CLK) (5.597:5.597:5.597))
(HOLD (negedge WEN[6]) (posedge CLK) (4.177:4.177:4.178))
(HOLD (posedge WEN[7]) (posedge CLK) (5.597:5.597:5.597))
(HOLD (negedge WEN[7]) (posedge CLK) (4.177:4.177:4.178))
(SETUP (posedge WEN[0]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[0]) (posedge CLK) (-2.213:-2.213:-2.214))
(SETUP (posedge WEN[1]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[1]) (posedge CLK) (-2.213:-2.213:-2.214))
(SETUP (posedge WEN[2]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[2]) (posedge CLK) (-2.213:-2.213:-2.214))
(SETUP (posedge WEN[3]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[3]) (posedge CLK) (-2.213:-2.213:-2.214))
(SETUP (posedge WEN[4]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[4]) (posedge CLK) (-2.213:-2.213:-2.214))
(SETUP (posedge WEN[5]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[5]) (posedge CLK) (-2.213:-2.213:-2.214))
(SETUP (posedge WEN[6]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[6]) (posedge CLK) (-2.213:-2.213:-2.214))
(SETUP (posedge WEN[7]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[7]) (posedge CLK) (-2.213:-2.213:-2.214))
(HOLD (posedge GWEN) (posedge CLK) (5.710:5.710:5.710))
(HOLD (negedge GWEN) (posedge CLK) (4.174:4.175:4.176))
(SETUP (posedge GWEN) (posedge CLK) (-1.602:-1.602:-1.603))
(SETUP (negedge GWEN) (posedge CLK) (-1.258:-1.259:-1.259))
(HOLD (posedge CEN) (posedge CLK) (10.992:10.992:10.992))
(HOLD (negedge CEN) (posedge CLK) (11.332:11.332:11.332))
(SETUP (posedge CEN) (posedge CLK) (1.390:1.390:1.390))
(SETUP (negedge CEN) (posedge CLK) (1.047:1.047:1.047))
(WIDTH (posedge CLK) (10.915:10.915:10.915))
(WIDTH (negedge CLK) (10.289:10.289:10.289))
(PERIOD CLK (22.470:22.470:22.470))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__buf_2")
(INSTANCE mod\.u_scanchain_local\.input_buf_clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.465:0.465:0.465) (0.386:0.386:0.386))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__dffnq_1")
(INSTANCE mod\.u_scanchain_local\.out_flop)
(DELAY
(ABSOLUTE
(IOPATH CLKN Q (1.009:1.009:1.009) (0.778:0.778:0.778))
)
)
(TIMINGCHECK
(SETUP (posedge D) (negedge CLKN) (0.190:0.190:0.190))
(SETUP (negedge D) (negedge CLKN) (0.341:0.341:0.341))
(HOLD (posedge D) (negedge CLKN) (0.143:0.143:0.143))
(HOLD (negedge D) (negedge CLKN) (-0.035:-0.035:-0.035))
(WIDTH (posedge CLKN) (0.406:0.406:0.406))
(WIDTH (negedge CLKN) (0.446:0.446:0.446))
(PERIOD CLKN (1.091:1.091:1.091))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__buf_4")
(INSTANCE mod\.u_scanchain_local\.output_buffers\[2\])
(DELAY
(ABSOLUTE
(IOPATH I Z (0.193:0.193:0.193) (0.234:0.234:0.234))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__buf_4")
(INSTANCE mod\.u_scanchain_local\.output_buffers\[3\])
(DELAY
(ABSOLUTE
(IOPATH I Z (0.141:0.141:0.141) (0.162:0.162:0.162))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[0\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.799:0.799:0.799) (0.808:0.808:0.808))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.799:0.799:0.799) (0.808:0.808:0.808)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.799:0.799:0.799) (0.808:0.808:0.808)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.799:0.799:0.799) (0.808:0.808:0.808)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.799:0.799:0.799) (0.808:0.808:0.808)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.492:0.493))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.571:0.590:0.608))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.492:0.493))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.571:0.590:0.608))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.108:-0.118:-0.129))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.108:-0.118:-0.129))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.886:1.886:1.886))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.205:0.205:0.205))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.169:2.169:2.169))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.670:-1.670:-1.670))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.270:0.270:0.270))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.507:0.507:0.507))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.652:0.652:0.652))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.507:0.507:0.507))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.652:0.652:0.652))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.143:-0.143:-0.143))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.143:-0.143:-0.143))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[10\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.028:1.028:1.028) (0.962:0.962:0.962))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.028:1.028:1.028) (0.962:0.962:0.962)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.028:1.028:1.028) (0.962:0.962:0.962)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.028:1.028:1.028) (0.962:0.962:0.962)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.028:1.028:1.028) (0.962:0.962:0.962)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.589:0.589:0.589))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.589:0.589:0.589))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.188:0.188:0.188))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.157:2.157:2.157))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.666:-1.666:-1.666))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.843:-0.843:-0.843))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[11\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.984:0.984:0.984) (0.934:0.934:0.934))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.984:0.984:0.984) (0.934:0.934:0.934)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.984:0.984:0.984) (0.934:0.934:0.934)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.984:0.984:0.984) (0.934:0.934:0.934)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.984:0.984:0.984) (0.934:0.934:0.934)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.188:0.188:0.188))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.157:2.157:2.157))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.666:-1.666:-1.666))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.843:-0.843:-0.843))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.584:0.584:0.584))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.584:0.584:0.584))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[12\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.057:1.057:1.057) (0.981:0.981:0.981))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.057:1.057:1.057) (0.981:0.981:0.981)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.057:1.057:1.057) (0.981:0.981:0.981)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.057:1.057:1.057) (0.981:0.981:0.981)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.057:1.057:1.057) (0.981:0.981:0.981)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.573:0.573:0.573))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.483:0.483:0.483))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.573:0.573:0.573))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.105:-0.105:-0.105))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.105:-0.105:-0.105))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.152:2.152:2.152))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.107:-0.107:-0.107))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.107:-0.107:-0.107))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[13\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.956:0.956:0.956) (0.914:0.914:0.914))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.956:0.956:0.956) (0.914:0.914:0.914)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.956:0.956:0.956) (0.914:0.914:0.914)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.956:0.956:0.956) (0.914:0.914:0.914)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.956:0.956:0.956) (0.914:0.914:0.914)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.110:-0.110:-0.110))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.192:0.192:0.192))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.851:-0.851:-0.851))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.593:0.593:0.593))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.593:0.593:0.593))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.119:-0.119:-0.119))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.119:-0.119:-0.119))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[14\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.994:0.994:0.994) (0.941:0.941:0.941))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.994:0.994:0.994) (0.941:0.941:0.941)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.994:0.994:0.994) (0.941:0.941:0.941)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.994:0.994:0.994) (0.941:0.941:0.941)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.994:0.994:0.994) (0.942:0.942:0.942)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.581:0.581:0.581))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.581:0.581:0.581))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.484:0.484:0.484))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.572:0.572:0.572))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.484:0.484:0.484))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.572:0.572:0.572))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.106:-0.106:-0.106))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.106:-0.106:-0.106))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[15\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.902:0.902:0.902) (0.878:0.878:0.878))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.902:0.902:0.902) (0.878:0.878:0.878)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.902:0.902:0.902) (0.878:0.878:0.878)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.902:0.902:0.902) (0.878:0.878:0.878)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.902:0.902:0.902) (0.878:0.878:0.878)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.563:0.563:0.563))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.563:0.563:0.563))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.110:-0.110:-0.110))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.882:1.882:1.882))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.192:0.192:0.192))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.167:2.167:2.167))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.670:-1.670:-1.670))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.854:-0.854:-0.854))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.587:0.587:0.587))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.587:0.587:0.587))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.116:-0.116:-0.116))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.116:-0.116:-0.116))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[16\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.980:0.980:0.980) (0.933:0.933:0.933))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.980:0.980:0.980) (0.933:0.933:0.933)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.980:0.980:0.980) (0.933:0.933:0.933)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.980:0.980:0.980) (0.933:0.933:0.933)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.980:0.980:0.980) (0.933:0.933:0.933)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.090:-0.090))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.090:-0.090))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.877:1.877:1.877))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.566:0.566:0.566))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.482:0.482:0.482))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.566:0.566:0.566))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[17\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.025:1.025:1.025) (0.958:0.958:0.958))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.025:1.025:1.025) (0.958:0.958:0.958)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.025:1.025:1.025) (0.958:0.958:0.958)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.025:1.025:1.025) (0.958:0.958:0.958)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.025:1.025:1.025) (0.958:0.958:0.958)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.110:-0.110:-0.110))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.192:0.192:0.192))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.164:2.164:2.164))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.851:-0.851:-0.851))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.583:0.583:0.583))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.583:0.583:0.583))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.114:-0.114:-0.114))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.114:-0.114:-0.114))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[18\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.800:0.800:0.800) (0.810:0.810:0.810))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.800:0.800:0.800) (0.810:0.810:0.810)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.800:0.800:0.800) (0.810:0.810:0.810)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.800:0.800:0.800) (0.810:0.810:0.810)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.800:0.800:0.800) (0.810:0.810:0.810)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.098:-0.098))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.098:-0.098))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.668:-1.668:-1.668))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.592:0.592:0.592))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.592:0.592:0.592))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.118:-0.118:-0.118))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.118:-0.118:-0.118))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[19\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.746:0.746:0.746) (0.773:0.773:0.773))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.746:0.746:0.746) (0.773:0.773:0.773)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.746:0.746:0.746) (0.773:0.773:0.773)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.746:0.746:0.746) (0.773:0.773:0.773)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.746:0.746:0.746) (0.773:0.773:0.773)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.668:-1.668:-1.668))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.566:0.566:0.566))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.566:0.566:0.566))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.105:-0.105:-0.105))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.105:-0.105:-0.105))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[1\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.941:0.941:0.941) (0.901:0.901:0.901))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.941:0.941:0.941) (0.901:0.901:0.901)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.941:0.941:0.941) (0.901:0.901:0.901)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.941:0.941:0.941) (0.901:0.901:0.901)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.941:0.941:0.941) (0.901:0.901:0.901)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.493:0.493:0.494))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.584:0.589:0.594))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.493:0.493:0.494))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.584:0.589:0.594))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.118:-0.120:-0.123))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.118:-0.120:-0.123))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.892:1.892:1.892))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.214:0.214:0.214))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.171:2.171:2.171))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.671:-1.671:-1.671))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.266:0.266:0.266))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.573:0.573:0.573))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.497:0.497:0.497))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.256:-0.256:-0.256))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.256:-0.256:-0.256))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[20\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.767:0.767:0.767) (0.789:0.789:0.789))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.767:0.767:0.767) (0.789:0.789:0.789)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.767:0.767:0.767) (0.789:0.789:0.789)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.767:0.767:0.767) (0.789:0.789:0.789)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.767:0.767:0.767) (0.789:0.789:0.789)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.098:-0.098))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.098:-0.098))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.110:-0.110:-0.110))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.191:0.191:0.191))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.851:-0.851:-0.851))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[21\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.975:0.975:0.975) (0.926:0.926:0.926))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.975:0.975:0.975) (0.926:0.926:0.926)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.975:0.975:0.975) (0.926:0.926:0.926)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.975:0.975:0.975) (0.926:0.926:0.926)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.975:0.975:0.975) (0.926:0.926:0.926)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.583:0.583:0.583))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.583:0.583:0.583))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.191:0.191:0.191))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.852:-0.852:-0.852))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.562:0.562:0.562))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.562:0.562:0.562))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.101:-0.101:-0.101))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.101:-0.101:-0.101))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[22\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.776:0.776:0.776) (0.797:0.797:0.797))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.776:0.776:0.776) (0.797:0.797:0.797)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.776:0.776:0.776) (0.797:0.797:0.797)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.776:0.776:0.776) (0.797:0.797:0.797)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.776:0.776:0.776) (0.797:0.797:0.797)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.484:0.484))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.579:0.579:0.579))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.484:0.484))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.579:0.579:0.579))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.108:-0.108:-0.108))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.108:-0.108:-0.108))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.152:2.152:2.152))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.665:-1.665:-1.665))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.107:-0.107:-0.107))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.107:-0.107:-0.107))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[23\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.090:1.090:1.090) (0.999:0.999:0.999))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.090:1.090:1.090) (0.999:0.999:0.999)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.090:1.090:1.090) (0.999:0.999:0.999)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.090:1.090:1.090) (0.999:0.999:0.999)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.090:1.090:1.090) (0.999:0.999:0.999)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.574:0.574:0.574))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.574:0.574:0.574))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.108:-0.108:-0.108))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.108:-0.108:-0.108))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.110:-0.110:-0.110))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.191:0.191:0.191))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.851:-0.851:-0.851))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.562:0.562:0.562))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.562:0.562:0.562))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.101:-0.101:-0.101))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.101:-0.101:-0.101))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[24\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.968:0.968:0.968) (0.922:0.922:0.922))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.968:0.968:0.968) (0.922:0.922:0.922)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.968:0.968:0.968) (0.922:0.922:0.922)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.968:0.968:0.968) (0.922:0.922:0.922)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.968:0.968:0.968) (0.922:0.922:0.922)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.572:0.572:0.572))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.572:0.572:0.572))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.107:-0.107:-0.107))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.107:-0.107:-0.107))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.110:-0.110:-0.110))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.191:0.191:0.191))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.851:-0.851:-0.851))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.499:0.499:0.499))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.598:0.598:0.598))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.499:0.499:0.499))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.598:0.598:0.598))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.121:-0.121:-0.121))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.121:-0.121:-0.121))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[25\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.055:1.055:1.055) (0.980:0.980:0.980))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.055:1.055:1.055) (0.980:0.980:0.980)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.055:1.055:1.055) (0.980:0.980:0.980)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.055:1.055:1.055) (0.980:0.980:0.980)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.055:1.055:1.055) (0.980:0.980:0.980)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.090:-0.090))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.090:-0.090))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.574:0.574:0.574))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.574:0.574:0.574))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.106:-0.106:-0.106))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.106:-0.106:-0.106))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[26\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.820:0.820:0.820) (0.827:0.827:0.827))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.820:0.820:0.820) (0.827:0.827:0.827)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.820:0.820:0.820) (0.827:0.827:0.827)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.820:0.820:0.820) (0.827:0.827:0.827)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.820:0.820:0.820) (0.827:0.827:0.827)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.093:-0.093:-0.093))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.093:-0.093:-0.093))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.583:0.583:0.583))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.583:0.583:0.583))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.112:-0.112:-0.112))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.112:-0.112:-0.112))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[27\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.101:1.101:1.101) (1.010:1.010:1.010))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.101:1.101:1.101) (1.010:1.010:1.010)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.101:1.101:1.101) (1.010:1.010:1.010)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.101:1.101:1.101) (1.010:1.010:1.010)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.101:1.101:1.101) (1.010:1.010:1.010)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.094:-0.094))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.094:-0.094))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[28\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.812:0.812:0.812) (0.820:0.820:0.820))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.812:0.812:0.812) (0.820:0.820:0.820)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.812:0.812:0.812) (0.820:0.820:0.820)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.812:0.812:0.812) (0.820:0.820:0.820)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.812:0.812:0.812) (0.820:0.820:0.820)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.090:-0.090))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.090:-0.090))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.189:0.189:0.189))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.157:2.157:2.157))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.666:-1.666:-1.666))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.843:-0.843:-0.843))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.593:0.593:0.593))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.593:0.593:0.593))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.117:-0.117:-0.117))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.117:-0.117:-0.117))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[29\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.976:0.976:0.976) (0.929:0.929:0.929))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.976:0.976:0.976) (0.929:0.929:0.929)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.976:0.976:0.976) (0.929:0.929:0.929)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.976:0.976:0.976) (0.929:0.929:0.929)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.976:0.976:0.976) (0.930:0.930:0.930)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.547:0.547:0.547))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.547:0.547:0.547))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[2\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.928:0.928:0.928) (0.895:0.895:0.895))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.928:0.928:0.928) (0.895:0.895:0.895)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.928:0.928:0.928) (0.895:0.895:0.895)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.928:0.928:0.928) (0.895:0.895:0.895)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.928:0.928:0.928) (0.895:0.895:0.895)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.569:0.573:0.578))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.569:0.573:0.578))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.106:-0.109:-0.111))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.106:-0.109:-0.111))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.668:-1.668:-1.668))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.582:0.582:0.582))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.582:0.582:0.582))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[30\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.819:0.819:0.819) (0.825:0.825:0.825))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.819:0.819:0.819) (0.825:0.825:0.825)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.819:0.819:0.819) (0.825:0.825:0.825)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.819:0.819:0.819) (0.825:0.825:0.825)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.819:0.819:0.819) (0.825:0.825:0.825)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.600:0.600:0.600))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.600:0.600:0.600))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.120:-0.120:-0.120))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.120:-0.120:-0.120))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.189:0.189:0.189))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.157:2.157:2.157))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.666:-1.666:-1.666))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.843:-0.843:-0.843))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.577:0.577:0.577))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.577:0.577:0.577))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[31\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.801:0.801:0.801) (0.814:0.814:0.814))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.801:0.801:0.801) (0.814:0.814:0.814)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.801:0.801:0.801) (0.814:0.814:0.814)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.801:0.801:0.801) (0.814:0.814:0.814)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.801:0.801:0.801) (0.814:0.814:0.814)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.098:-0.098))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.098:-0.098))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[32\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.901:0.901:0.901) (0.881:0.881:0.881))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.901:0.901:0.901) (0.881:0.881:0.881)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.901:0.901:0.901) (0.881:0.881:0.881)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.901:0.901:0.901) (0.881:0.881:0.881)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.901:0.901:0.901) (0.881:0.881:0.881)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.546:0.546:0.546))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.546:0.546:0.546))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.242:-0.242:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[33\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.827:0.827:0.827) (0.831:0.831:0.831))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.827:0.827:0.827) (0.831:0.831:0.831)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.827:0.827:0.827) (0.831:0.831:0.831)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.827:0.827:0.827) (0.831:0.831:0.831)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.827:0.827:0.827) (0.831:0.831:0.831)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.877:1.877:1.877))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.565:0.565:0.565))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.565:0.565:0.565))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.101:-0.101:-0.101))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.101:-0.101:-0.101))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[34\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.612:0.612:0.612) (0.669:0.669:0.669))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.612:0.612:0.612) (0.669:0.669:0.669)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.612:0.612:0.612) (0.669:0.669:0.669)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.612:0.612:0.612) (0.669:0.669:0.669)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.612:0.612:0.612) (0.669:0.669:0.669)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.088:-0.088:-0.088))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.243:-0.243))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.088:-0.088:-0.088))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.877:1.877:1.877))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.480:0.480:0.480))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[35\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.609:0.609:0.609) (0.665:0.665:0.665))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.609:0.609:0.609) (0.665:0.665:0.665)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.609:0.609:0.609) (0.665:0.665:0.665)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.609:0.609:0.609) (0.665:0.665:0.665)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.609:0.609:0.609) (0.665:0.665:0.665)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.110:-0.110:-0.110))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.192:0.192:0.192))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.851:-0.851:-0.851))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.548:0.548:0.548))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.548:0.548:0.548))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.089:-0.089:-0.089))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.089:-0.089:-0.089))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[36\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.770:0.770:0.770) (0.793:0.793:0.793))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.770:0.770:0.770) (0.793:0.793:0.793)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.770:0.770:0.770) (0.793:0.793:0.793)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.770:0.770:0.770) (0.793:0.793:0.793)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.770:0.770:0.770) (0.793:0.793:0.793)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.479:0.479))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.151:2.151:2.151))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.277:0.277:0.277))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.541:0.541:0.541))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.541:0.541:0.541))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.082:-0.082:-0.082))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[37\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.721:0.721:0.721) (0.755:0.755:0.755))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.721:0.721:0.721) (0.755:0.755:0.755)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.721:0.721:0.721) (0.755:0.755:0.755)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.721:0.721:0.721) (0.755:0.755:0.755)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.721:0.721:0.721) (0.755:0.755:0.755)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.572:0.572:0.572))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.572:0.572:0.572))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.107:-0.107:-0.107))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.107:-0.107:-0.107))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.110:-0.110:-0.110))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.192:0.192:0.192))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.164:2.164:2.164))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.851:-0.851:-0.851))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.101:-0.101:-0.101))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.101:-0.101:-0.101))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[38\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.598:0.598:0.598) (0.655:0.655:0.655))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.598:0.598:0.598) (0.655:0.655:0.655)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.598:0.598:0.598) (0.655:0.655:0.655)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.598:0.598:0.598) (0.655:0.655:0.655)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.598:0.598:0.598) (0.655:0.655:0.655)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.892:1.892:1.892))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.214:0.214:0.214))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.171:2.171:2.171))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.671:-1.671:-1.671))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.266:0.266:0.266))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.567:0.567:0.567))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.569:0.569:0.569))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.256:-0.256:-0.256))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.106:-0.106:-0.106))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.256:-0.256:-0.256))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.106:-0.106:-0.106))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[39\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.564:0.564:0.564))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.564:0.564:0.564))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.892:1.892:1.892))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.214:0.214:0.214))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.171:2.171:2.171))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.671:-1.671:-1.671))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.266:0.266:0.266))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[3\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.025:1.025:1.025) (0.957:0.957:0.957))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.025:1.025:1.025) (0.957:0.957:0.957)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.025:1.025:1.025) (0.957:0.957:0.957)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.025:1.025:1.025) (0.957:0.957:0.957)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.025:1.025:1.025) (0.957:0.957:0.957)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.487:0.489))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.576:0.591))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.487:0.489))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.576:0.591))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.248:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.099:-0.108:-0.118))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.248:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.099:-0.108:-0.118))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.110:-0.110:-0.110))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.882:1.882:1.882))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.192:0.192:0.192))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.168:2.168:2.168))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.670:-1.670:-1.670))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.854:-0.854:-0.854))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.580:0.580:0.580))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.580:0.580:0.580))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.112:-0.112:-0.112))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.112:-0.112:-0.112))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[40\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.483:0.485:0.487))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.558:0.562))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.483:0.485:0.487))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.558:0.562))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.247:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.093:-0.096:-0.099))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.247:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.093:-0.096:-0.099))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.668:-1.668:-1.668))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.093:-0.093:-0.093))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.093:-0.093:-0.093))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[41\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.625:0.625:0.625) (0.678:0.678:0.678))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.625:0.625:0.625) (0.678:0.678:0.678)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.625:0.625:0.625) (0.678:0.678:0.678)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.625:0.625:0.625) (0.678:0.678:0.678)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.625:0.625:0.625) (0.678:0.678:0.678)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.486:0.487))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.557:0.562))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.486:0.487))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.557:0.562))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.246:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.091:-0.095:-0.099))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.091:-0.095:-0.099))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.668:-1.668:-1.668))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[42\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.625:0.625:0.625) (0.679:0.679:0.679))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.625:0.625:0.625) (0.679:0.679:0.679)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.625:0.625:0.625) (0.679:0.679:0.679)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.625:0.625:0.625) (0.679:0.679:0.679)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.625:0.625:0.625) (0.679:0.679:0.679)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.486:0.488))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.552:0.574:0.596))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.486:0.488))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.552:0.574:0.596))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.248:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.105:-0.120))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.105:-0.120))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.166:2.166:2.166))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.094:-0.094:-0.094))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.094:-0.094:-0.094))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[43\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.608:0.608:0.608) (0.663:0.663:0.663))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.608:0.608:0.608) (0.663:0.663:0.663)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.608:0.608:0.608) (0.663:0.663:0.663)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.608:0.608:0.608) (0.663:0.663:0.663)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.608:0.608:0.608) (0.663:0.663:0.663)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.490:0.492))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.579:0.601))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.490:0.492))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.579:0.601))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.109:-0.125))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.109:-0.125))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.885:1.885:1.885))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.201:0.201:0.201))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.169:2.169:2.169))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.670:-1.670:-1.670))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.272:0.272:0.272))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.856:-0.856:-0.856))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[44\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.617:0.617:0.617) (0.673:0.673:0.673))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.617:0.617:0.617) (0.673:0.673:0.673)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.617:0.617:0.617) (0.673:0.673:0.673)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.617:0.617:0.617) (0.673:0.673:0.673)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.617:0.617:0.617) (0.673:0.673:0.673)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.480:0.481))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.547:0.550:0.553))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.479:0.480:0.481))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.547:0.550:0.553))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.086:-0.089:-0.092))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.244:-0.244))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.086:-0.089:-0.092))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.189:0.189:0.189))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.155:2.155:2.155))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.665:-1.665:-1.665))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.842:-0.842:-0.842))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.544:0.544:0.544))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.544:0.544:0.544))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[45\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.480:0.482))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.543:0.564:0.585))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.480:0.482))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.543:0.564:0.585))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.083:-0.098:-0.112))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.083:-0.098:-0.112))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.189:0.189:0.189))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.156:2.156:2.156))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.665:-1.665:-1.665))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.842:-0.842:-0.842))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.544:0.544:0.544))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.544:0.544:0.544))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[46\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.625:0.625:0.625) (0.681:0.681:0.681))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.625:0.625:0.625) (0.681:0.681:0.681)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.625:0.625:0.625) (0.681:0.681:0.681)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.625:0.625:0.625) (0.681:0.681:0.681)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.625:0.625:0.625) (0.681:0.681:0.681)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.475:0.477:0.478))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.540:0.545:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.475:0.477:0.478))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.540:0.545:0.550))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.243:-0.242))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.080:-0.084:-0.089))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.243:-0.242))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.080:-0.084:-0.089))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.877:1.877:1.877))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.150:2.150:2.150))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.541:0.541:0.541))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.541:0.541:0.541))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.083:-0.083:-0.083))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.083:-0.083:-0.083))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[47\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.620:0.620:0.620) (0.675:0.675:0.675))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.620:0.620:0.620) (0.675:0.675:0.675)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.620:0.620:0.620) (0.675:0.675:0.675)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.620:0.620:0.620) (0.675:0.675:0.675)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.620:0.620:0.620) (0.675:0.675:0.675)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.480:0.482))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.544:0.565:0.586))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.478:0.480:0.482))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.544:0.565:0.586))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.246))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.083:-0.098:-0.113))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.246))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.083:-0.098:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.878:1.878:1.878))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.189:0.189:0.189))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.156:2.156:2.156))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.665:-1.665:-1.665))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.842:-0.842:-0.842))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.481:0.481:0.481))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.246:-0.246:-0.246))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.086:-0.086:-0.086))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[48\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.623:0.623:0.623) (0.679:0.679:0.679))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.623:0.623:0.623) (0.679:0.679:0.679)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.623:0.623:0.623) (0.679:0.679:0.679)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.623:0.623:0.623) (0.679:0.679:0.679)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.623:0.623:0.623) (0.679:0.679:0.679)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.476:0.478:0.480))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.541:0.565:0.589))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.476:0.478:0.480))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.541:0.565:0.589))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.246:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.081:-0.097:-0.113))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.243:-0.246:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.081:-0.097:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.115:-0.115:-0.115))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.877:1.877:1.877))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.187:0.187:0.187))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.150:2.150:2.150))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.664:-1.664:-1.664))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.837:-0.837:-0.837))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.541:0.541:0.541))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.541:0.541:0.541))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.083:-0.083:-0.083))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.245:-0.245:-0.245))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.083:-0.083:-0.083))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[49\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.492:0.495))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.559:0.584:0.608))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.492:0.495))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.559:0.584:0.608))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.250:-0.252))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.097:-0.113:-0.129))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.250:-0.252))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.097:-0.113:-0.129))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.886:1.886:1.886))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.201:0.201:0.201))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.170:2.170:2.170))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.671:-1.671:-1.671))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.272:0.272:0.272))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.856:-0.856:-0.856))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[4\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.038:1.038:1.038) (0.968:0.968:0.968))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.038:1.038:1.038) (0.968:0.968:0.968)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.038:1.038:1.038) (0.968:0.968:0.968)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.038:1.038:1.038) (0.968:0.968:0.968)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.038:1.038:1.038) (0.968:0.968:0.968)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.481:0.482:0.483))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.570:0.585))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.481:0.482:0.483))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.570:0.585))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.246:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.103:-0.112))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.246:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.103:-0.112))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.188:0.188:0.188))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.157:2.157:2.157))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.666:-1.666:-1.666))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.843:-0.843:-0.843))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.585:0.585:0.585))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.585:0.585:0.585))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[50\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.621:0.621:0.621) (0.674:0.674:0.674))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.674:0.674:0.674)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.674:0.674:0.674)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.674:0.674:0.674)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.674:0.674:0.674)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.490:0.492))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.579:0.602))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.490:0.492))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.579:0.602))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.110:-0.125))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.110:-0.125))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.884:1.884:1.884))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.201:0.201:0.201))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.167:2.167:2.167))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.272:0.272:0.272))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.095:-0.095:-0.095))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[51\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.642:0.642:0.642) (0.693:0.693:0.693))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.642:0.642:0.642) (0.693:0.693:0.693)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.642:0.642:0.642) (0.693:0.693:0.693)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.642:0.642:0.642) (0.693:0.693:0.693)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.642:0.642:0.642) (0.693:0.693:0.693)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.492:0.496))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.560:0.586:0.613))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.492:0.496))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.560:0.586:0.613))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.250:-0.252))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.114:-0.130))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.250:-0.252))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.114:-0.130))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.886:1.886:1.886))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.201:0.201:0.201))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.170:2.170:2.170))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.671:-1.671:-1.671))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.272:0.272:0.272))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.856:-0.856:-0.856))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[52\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.491:0.494))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.579:0.600))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.491:0.494))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.579:0.600))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.250:-0.252))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.110:-0.124))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.250:-0.252))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.095:-0.110:-0.124))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.884:1.884:1.884))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.201:0.201:0.201))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.167:2.167:2.167))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.272:0.272:0.272))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[53\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.600:0.600:0.600) (0.656:0.656:0.656))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.600:0.600:0.600) (0.656:0.656:0.656)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.600:0.600:0.600) (0.656:0.656:0.656)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.600:0.600:0.600) (0.656:0.656:0.656)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.600:0.600:0.600) (0.656:0.656:0.656)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.491:0.493))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.583:0.607))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.491:0.493))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.583:0.607))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.250:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.112:-0.128))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.250:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.112:-0.128))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.884:1.884:1.884))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.201:0.201:0.201))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.167:2.167:2.167))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.272:0.272:0.272))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[54\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.614:0.614:0.614) (0.668:0.668:0.668))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.614:0.614:0.614) (0.668:0.668:0.668)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.614:0.614:0.614) (0.668:0.668:0.668)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.614:0.614:0.614) (0.668:0.668:0.668)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.614:0.614:0.614) (0.668:0.668:0.668)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.492:0.495))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.559:0.583:0.607))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.492:0.495))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.559:0.583:0.607))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.250:-0.252))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.097:-0.112:-0.128))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.250:-0.252))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.097:-0.112:-0.128))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.884:1.884:1.884))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.201:0.201:0.201))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.167:2.167:2.167))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.272:0.272:0.272))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.094:-0.094:-0.094))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.094:-0.094:-0.094))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[55\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.639:0.639:0.639) (0.691:0.691:0.691))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.639:0.639:0.639) (0.691:0.691:0.691)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.639:0.639:0.639) (0.691:0.691:0.691)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.639:0.639:0.639) (0.691:0.691:0.691)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.639:0.639:0.639) (0.691:0.691:0.691)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.488:0.491))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.576:0.598))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.488:0.491))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.576:0.598))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.249:-0.252))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.092:-0.107:-0.122))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.249:-0.252))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.092:-0.107:-0.122))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.164:2.164:2.164))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.667:-1.667:-1.667))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.093:-0.093:-0.093))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.093:-0.093:-0.093))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[56\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.606:0.606:0.606) (0.662:0.662:0.662))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.606:0.606:0.606) (0.662:0.662:0.662)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.606:0.606:0.606) (0.662:0.662:0.662)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.606:0.606:0.606) (0.662:0.662:0.662)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.606:0.606:0.606) (0.662:0.662:0.662)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.490:0.492))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.581:0.604))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.490:0.492))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.581:0.604))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.111:-0.126))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.111:-0.126))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.102:-0.102:-0.102))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.884:1.884:1.884))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.201:0.201:0.201))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.167:2.167:2.167))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.272:0.272:0.272))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[57\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.605:0.605:0.605) (0.661:0.661:0.661)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.489:0.493))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.583:0.609))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.489:0.493))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.583:0.609))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.248:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.110:-0.127))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.248:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.110:-0.127))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.164:2.164:2.164))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.667:-1.667:-1.667))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.092:-0.092:-0.092))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.092:-0.092:-0.092))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[58\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.636:0.636:0.636) (0.688:0.688:0.688))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.636:0.636:0.636) (0.688:0.688:0.688)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.636:0.636:0.636) (0.688:0.688:0.688)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.636:0.636:0.636) (0.688:0.688:0.688)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.636:0.636:0.636) (0.688:0.688:0.688)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.489:0.492))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.581:0.606))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.489:0.492))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.581:0.606))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.248:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.110:-0.126))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.248:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.110:-0.126))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.164:2.164:2.164))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.667:-1.667:-1.667))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[59\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.604:0.604:0.604) (0.661:0.661:0.661))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.604:0.604:0.604) (0.661:0.661:0.661)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.604:0.604:0.604) (0.661:0.661:0.661)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.604:0.604:0.604) (0.661:0.661:0.661)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.604:0.604:0.604) (0.661:0.661:0.661)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.486:0.488))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.552:0.573:0.594))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.486:0.488))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.552:0.573:0.594))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.248:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.105:-0.120))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.090:-0.105:-0.120))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.163:2.163:2.163))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.667:-1.667:-1.667))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.852:-0.852:-0.852))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[5\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.964:0.964:0.964) (0.921:0.921:0.921))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.964:0.964:0.964) (0.921:0.921:0.921)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.964:0.964:0.964) (0.921:0.921:0.921)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.964:0.964:0.964) (0.921:0.921:0.921)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.965:0.965:0.965) (0.921:0.921:0.921)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.482:0.482:0.483))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.573:0.589))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.482:0.482:0.483))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.573:0.589))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.246:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.105:-0.114))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.244:-0.246:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.105:-0.114))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.188:0.188:0.188))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.157:2.157:2.157))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.666:-1.666:-1.666))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.843:-0.843:-0.843))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.585:0.585:0.585))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.585:0.585:0.585))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[60\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.488:0.491))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.576:0.598))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.485:0.488:0.491))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.576:0.598))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.249:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.092:-0.107:-0.122))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.249:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.092:-0.107:-0.122))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.163:2.163:2.163))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.667:-1.667:-1.667))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.852:-0.852:-0.852))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[61\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.607:0.607:0.607) (0.663:0.663:0.663))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.607:0.607:0.607) (0.663:0.663:0.663)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.607:0.607:0.607) (0.663:0.663:0.663)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.607:0.607:0.607) (0.663:0.663:0.663)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.607:0.607:0.607) (0.663:0.663:0.663)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.492:0.494))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.580:0.602))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.489:0.492:0.494))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.558:0.580:0.602))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.251:-0.252))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.111:-0.125))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.251:-0.252))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.096:-0.111:-0.125))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.886:1.886:1.886))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.205:0.205:0.205))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.168:2.168:2.168))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.270:0.270:0.270))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.097:-0.097:-0.097))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[62\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.608:0.608:0.608) (0.664:0.664:0.664))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.608:0.608:0.608) (0.664:0.664:0.664)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.608:0.608:0.608) (0.664:0.664:0.664)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.608:0.608:0.608) (0.664:0.664:0.664)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.608:0.608:0.608) (0.664:0.664:0.664)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.487:0.489))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.575:0.597))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.487:0.489))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.575:0.597))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.248:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.092:-0.107:-0.122))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.248:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.092:-0.107:-0.122))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.164:2.164:2.164))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.667:-1.667:-1.667))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.092:-0.092:-0.092))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.092:-0.092:-0.092))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[63\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.676:0.676:0.676)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.488:0.490))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.580:0.605))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.488:0.490))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.580:0.605))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.248:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.093:-0.109:-0.125))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.246:-0.248:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.093:-0.109:-0.125))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.164:2.164:2.164))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.667:-1.667:-1.667))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.092:-0.092:-0.092))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.092:-0.092:-0.092))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[64\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.610:0.610:0.610) (0.666:0.666:0.666))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.610:0.610:0.610) (0.666:0.666:0.666)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.610:0.610:0.610) (0.666:0.666:0.666)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.610:0.610:0.610) (0.666:0.666:0.666)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.610:0.610:0.610) (0.666:0.666:0.666)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.487:0.490))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.576:0.598))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.484:0.487:0.490))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.576:0.598))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.249:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.092:-0.107:-0.122))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.249:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.092:-0.107:-0.122))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.193:0.193:0.193))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.164:2.164:2.164))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.667:-1.667:-1.667))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.275:0.275:0.275))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.853:-0.853:-0.853))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.487:0.487:0.487))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.094:-0.094:-0.094))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.094:-0.094:-0.094))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[65\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.604:0.604:0.604) (0.659:0.659:0.659))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.604:0.604:0.604) (0.659:0.659:0.659)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.604:0.604:0.604) (0.659:0.659:0.659)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.604:0.604:0.604) (0.659:0.659:0.659)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.604:0.604:0.604) (0.659:0.659:0.659)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.492:0.494:0.496))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.585:0.609))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.492:0.494:0.496))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.585:0.609))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.251:-0.252))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.099:-0.115:-0.130))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.251:-0.252))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.099:-0.115:-0.130))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.891:1.891:1.891))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.214:0.214:0.214))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.170:2.170:2.170))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.670:-1.670:-1.670))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.265:0.265:0.265))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.854:-0.854:-0.854))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.098:-0.098:-0.098))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.098:-0.098:-0.098))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[66\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.610:0.610:0.610) (0.665:0.665:0.665)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.492:0.494))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.560:0.585:0.611))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.492:0.494))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.560:0.585:0.611))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.250:-0.252))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.097:-0.114:-0.130))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.250:-0.252))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.097:-0.114:-0.130))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.886:1.886:1.886))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.205:0.205:0.205))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.168:2.168:2.168))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.270:0.270:0.270))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.854:-0.854:-0.854))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[67\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.621:0.621:0.621) (0.675:0.675:0.675)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.490:0.492))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.578:0.599))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.490:0.492))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.578:0.599))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.109:-0.124))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.094:-0.109:-0.124))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.099:-0.099:-0.099))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.886:1.886:1.886))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.205:0.205:0.205))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.169:2.169:2.169))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.670:-1.670:-1.670))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.270:0.270:0.270))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.491:0.491:0.491))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.096:-0.096:-0.096))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[68\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.619:0.619:0.619) (0.673:0.673:0.673)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.492:0.493))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.574:0.587))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.491:0.492:0.493))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.561:0.574:0.587))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.109:-0.119))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.098:-0.109:-0.119))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.891:1.891:1.891))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.214:0.214:0.214))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.170:2.170:2.170))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.671:-1.671:-1.671))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.266:0.266:0.266))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.854:-0.854:-0.854))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[69\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.877:0.877:0.877) (0.859:0.859:0.859))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.877:0.877:0.877) (0.859:0.859:0.859)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.877:0.877:0.877) (0.859:0.859:0.859)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.877:0.877:0.877) (0.859:0.859:0.859)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.877:0.877:0.877) (0.859:0.859:0.859)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.492:0.493:0.494))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.562:0.576:0.590))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.492:0.493:0.494))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.562:0.576:0.590))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.251:-0.251))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.100:-0.110:-0.120))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.100:-0.110:-0.120))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.091:-0.091:-0.091))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.892:1.892:1.892))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.214:0.214:0.214))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.171:2.171:2.171))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.671:-1.671:-1.671))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.266:0.266:0.266))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.855:-0.855:-0.855))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.252:-0.252:-0.252))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.100:-0.100:-0.100))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[6\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.912:0.912:0.912) (0.887:0.887:0.887))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.912:0.912:0.912) (0.887:0.887:0.887)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.912:0.912:0.912) (0.887:0.887:0.887)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.912:0.912:0.912) (0.887:0.887:0.887)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.912:0.912:0.912) (0.887:0.887:0.887)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.188:0.188:0.188))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.157:2.157:2.157))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.666:-1.666:-1.666))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.843:-0.843:-0.843))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.576:0.576:0.576))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.488:0.488:0.488))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.576:0.576:0.576))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[7\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.040:1.040:1.040) (0.967:0.967:0.967))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.040:1.040:1.040) (0.967:0.967:0.967)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.040:1.040:1.040) (0.967:0.967:0.967)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.040:1.040:1.040) (0.967:0.967:0.967)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.040:1.040:1.040) (0.967:0.967:0.967)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.593:0.593:0.593))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.493:0.493:0.493))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.593:0.593:0.593))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.119:-0.119:-0.119))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.249:-0.249:-0.249))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.119:-0.119:-0.119))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.191:0.191:0.191))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.852:-0.852:-0.852))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[8\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.912:0.912:0.912) (0.887:0.887:0.887))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.912:0.912:0.912) (0.888:0.888:0.888)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.912:0.912:0.912) (0.887:0.887:0.887)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.912:0.912:0.912) (0.887:0.887:0.887)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.912:0.912:0.912) (0.888:0.888:0.888)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.578:0.578:0.578))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.486:0.486:0.486))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.578:0.578:0.578))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.108:-0.108:-0.108))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.248:-0.248:-0.248))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.108:-0.108:-0.108))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.113:-0.113:-0.113))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.879:1.879:1.879))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.188:0.188:0.188))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.157:2.157:2.157))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.494:0.494:0.494))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.666:-1.666:-1.666))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.843:-0.843:-0.843))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.492:0.492:0.492))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.586:0.586:0.586))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.114:-0.114:-0.114))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.247:-0.247:-0.247))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.114:-0.114:-0.114))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE mod\.u_scanchain_local\.scan_flop\[9\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.808:0.808:0.808) (0.816:0.816:0.816))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.808:0.808:0.808) (0.816:0.816:0.816)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.808:0.808:0.808) (0.816:0.816:0.816)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.808:0.808:0.808) (0.816:0.816:0.816)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.808:0.808:0.808) (0.816:0.816:0.816)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.579:0.579:0.579))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.490:0.490:0.490))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.579:0.579:0.579))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.250:-0.250:-0.250))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.111:-0.111:-0.111))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.191:0.191:0.191))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (2.165:2.165:2.165))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.495:0.495:0.495))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.669:-1.669:-1.669))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.276:0.276:0.276))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.852:-0.852:-0.852))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.489:0.489:0.489))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.575:0.575:0.575))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.251:-0.251:-0.251))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.109:-0.109:-0.109))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_0_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.457:0.457:0.457) (0.441:0.441:0.441))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_3_0__f_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.314:0.314:0.314) (0.326:0.326:0.326))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_3_1__f_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.321:0.321:0.321) (0.333:0.333:0.333))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_3_2__f_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.297:0.297:0.297) (0.307:0.307:0.307))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_3_3__f_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.288:0.288:0.288) (0.297:0.297:0.297))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_3_4__f_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.339:0.339:0.339) (0.353:0.353:0.353))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_3_5__f_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.349:0.349:0.349) (0.363:0.363:0.363))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_3_6__f_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.313:0.313:0.313) (0.324:0.324:0.324))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_3_7__f_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.301:0.301:0.301) (0.311:0.311:0.311))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_opt_1_0_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.261:0.261:0.261) (0.262:0.262:0.262))
)
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__clkbuf_16")
(INSTANCE clkbuf_opt_1_1_mod\.u_scanchain_local\.clk)
(DELAY
(ABSOLUTE
(IOPATH I Z (0.225:0.225:0.225) (0.223:0.223:0.223))
)
)
)
)