| commit | f3ef131fcc93a278b2a00c57028037ebdc8d7c0d | [log] [tgz] | 
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 14 22:13:18 2022 -0800 | 
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Wed Dec 14 22:13:18 2022 -0800 | 
| tree | 5c8345a65c9fc48f15e9d424ba9723a0b69549a7 | |
| parent | adc25d0fbbbac2021b4e5ebc2d244b83c8451965 [diff] | 
update repo
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.