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foss-eda-tools/third_party/shuttle/gf180mcu/mpw-000/slot-001/dc24d54a166d86ae4896e1a7b0fdb6d12f3c3582/./sdf/serv_0.sdf
blob: 981a9948a5bc539636ae0bfc5ad0097e1ace9fc6 [file]
(DELAYFILE
(SDFVERSION "3.0")
(DESIGN "serv_0")
(DATE "Sun Dec 4 20:52:14 2022")
(VENDOR "Parallax")
(PROGRAM "STA")
(VERSION "2.3.2")
(DIVIDER .)
(TIMESCALE 1ns)
(CELL
(CELLTYPE "serv_0")
(INSTANCE)
(DELAY
(ABSOLUTE
(INTERCONNECT io_in[0] u_scanchain_local\.input_buf_clk.I (0.189:0.189:0.189) (0.119:0.119:0.119))
(INTERCONNECT io_in[0] ANTENNA_u_scanchain_local\.input_buf_clk_I.I (0.189:0.189:0.189) (0.118:0.118:0.118))
(INTERCONNECT io_in[1] _1403_.I (0.139:0.139:0.139) (0.087:0.087:0.087))
(INTERCONNECT io_in[1] ANTENNA__1403__I.I (0.139:0.139:0.139) (0.087:0.087:0.087))
(INTERCONNECT io_in[2] u_scanchain_local\.scan_flop\[0\].D (0.201:0.201:0.201) (0.126:0.126:0.126))
(INTERCONNECT io_in[2] ANTENNA_u_scanchain_local\.scan_flop\[0\]_D.I (0.202:0.202:0.202) (0.126:0.126:0.126))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[17\].SE (7.458:7.458:7.458) (4.729:4.729:4.729))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[28\].SE (7.457:7.457:7.457) (4.728:4.728:4.728))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[32\].SE (7.453:7.453:7.453) (4.724:4.724:4.724))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[31\].SE (7.457:7.457:7.457) (4.728:4.728:4.728))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[57\].SE (7.403:7.403:7.403) (4.675:4.675:4.675))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[69\].SE (7.423:7.423:7.423) (4.695:4.695:4.695))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[68\].SE (7.426:7.426:7.426) (4.697:4.697:4.697))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[56\].SE (7.402:7.402:7.402) (4.673:4.673:4.673))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[59\].SE (7.414:7.414:7.414) (4.685:4.685:4.685))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[58\].SE (7.408:7.408:7.408) (4.680:4.680:4.680))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[67\].SE (7.429:7.429:7.429) (4.700:4.700:4.700))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[66\].SE (7.437:7.437:7.437) (4.709:4.709:4.709))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[65\].SE (7.438:7.438:7.438) (4.709:4.709:4.709))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[64\].SE (7.438:7.438:7.438) (4.709:4.709:4.709))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[63\].SE (7.409:7.409:7.409) (4.681:4.681:4.681))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[62\].SE (7.438:7.438:7.438) (4.709:4.709:4.709))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[61\].SE (7.409:7.409:7.409) (4.681:4.681:4.681))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[60\].SE (7.409:7.409:7.409) (4.680:4.680:4.680))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[6\].SE (7.405:7.405:7.405) (4.676:4.676:4.676))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[9\].SE (7.431:7.431:7.431) (4.703:4.703:4.703))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[8\].SE (7.423:7.423:7.423) (4.695:4.695:4.695))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[7\].SE (7.431:7.431:7.431) (4.703:4.703:4.703))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[36\].SE (7.437:7.437:7.437) (4.708:4.708:4.708))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[37\].SE (7.445:7.445:7.445) (4.717:4.717:4.717))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[12\].SE (7.451:7.451:7.451) (4.722:4.722:4.722))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[13\].SE (7.451:7.451:7.451) (4.722:4.722:4.722))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[35\].SE (7.442:7.442:7.442) (4.714:4.714:4.714))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[10\].SE (7.431:7.431:7.431) (4.702:4.702:4.702))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[34\].SE (7.442:7.442:7.442) (4.714:4.714:4.714))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[11\].SE (7.431:7.431:7.431) (4.703:4.703:4.703))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[53\].SE (7.389:7.389:7.389) (4.660:4.660:4.660))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[1\].SE (7.366:7.366:7.366) (4.637:4.637:4.637))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[0\].SE (7.365:7.365:7.365) (4.637:4.637:4.637))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[2\].SE (7.405:7.405:7.405) (4.676:4.676:4.676))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[3\].SE (7.405:7.405:7.405) (4.677:4.677:4.677))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[4\].SE (7.405:7.405:7.405) (4.677:4.677:4.677))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[5\].SE (7.405:7.405:7.405) (4.677:4.677:4.677))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[38\].SE (7.405:7.405:7.405) (4.676:4.676:4.676))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[54\].SE (7.401:7.401:7.401) (4.672:4.672:4.672))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[52\].SE (7.385:7.385:7.385) (4.657:4.657:4.657))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[51\].SE (7.370:7.370:7.370) (4.641:4.641:4.641))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[41\].SE (7.361:7.361:7.361) (4.632:4.632:4.632))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[55\].SE (7.395:7.395:7.395) (4.666:4.666:4.666))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[39\].SE (7.404:7.404:7.404) (4.676:4.676:4.676))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[40\].SE (7.361:7.361:7.361) (4.632:4.632:4.632))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[49\].SE (7.364:7.364:7.364) (4.635:4.635:4.635))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[48\].SE (7.364:7.364:7.364) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[47\].SE (7.364:7.364:7.364) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[46\].SE (7.364:7.364:7.364) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[45\].SE (7.365:7.365:7.365) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[44\].SE (7.365:7.365:7.365) (4.637:4.637:4.637))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[43\].SE (7.364:7.364:7.364) (4.635:4.635:4.635))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[42\].SE (7.360:7.360:7.360) (4.632:4.632:4.632))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[50\].SE (7.361:7.361:7.361) (4.632:4.632:4.632))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[29\].SE (7.457:7.457:7.457) (4.728:4.728:4.728))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[30\].SE (7.455:7.455:7.455) (4.726:4.726:4.726))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[33\].SE (7.453:7.453:7.453) (4.724:4.724:4.724))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[16\].SE (7.456:7.456:7.456) (4.728:4.728:4.728))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[15\].SE (7.455:7.455:7.455) (4.726:4.726:4.726))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[14\].SE (7.451:7.451:7.451) (4.722:4.722:4.722))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[26\].SE (7.460:7.460:7.460) (4.731:4.731:4.731))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[25\].SE (7.462:7.462:7.462) (4.733:4.733:4.733))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[24\].SE (7.462:7.462:7.462) (4.733:4.733:4.733))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[23\].SE (7.461:7.461:7.461) (4.732:4.732:4.732))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[21\].SE (7.462:7.462:7.462) (4.733:4.733:4.733))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[20\].SE (7.462:7.462:7.462) (4.733:4.733:4.733))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[19\].SE (7.461:7.461:7.461) (4.732:4.732:4.732))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[18\].SE (7.461:7.461:7.461) (4.732:4.732:4.732))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[22\].SE (7.461:7.461:7.461) (4.732:4.732:4.732))
(INTERCONNECT io_in[3] u_scanchain_local\.scan_flop\[27\].SE (7.459:7.459:7.459) (4.730:4.730:4.730))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[27\]_SE.I (7.457:7.457:7.457) (4.728:4.728:4.728))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[22\]_SE.I (7.461:7.461:7.461) (4.732:4.732:4.732))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[18\]_SE.I (7.461:7.461:7.461) (4.732:4.732:4.732))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[19\]_SE.I (7.461:7.461:7.461) (4.732:4.732:4.732))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[20\]_SE.I (7.461:7.461:7.461) (4.732:4.732:4.732))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[21\]_SE.I (7.460:7.460:7.460) (4.731:4.731:4.731))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[23\]_SE.I (7.459:7.459:7.459) (4.730:4.730:4.730))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[24\]_SE.I (7.460:7.460:7.460) (4.731:4.731:4.731))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[25\]_SE.I (7.460:7.460:7.460) (4.731:4.731:4.731))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[26\]_SE.I (7.459:7.459:7.459) (4.730:4.730:4.730))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[14\]_SE.I (7.451:7.451:7.451) (4.722:4.722:4.722))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[15\]_SE.I (7.450:7.450:7.450) (4.721:4.721:4.721))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[16\]_SE.I (7.453:7.453:7.453) (4.724:4.724:4.724))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[33\]_SE.I (7.442:7.442:7.442) (4.713:4.713:4.713))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[30\]_SE.I (7.449:7.449:7.449) (4.720:4.720:4.720))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[29\]_SE.I (7.453:7.453:7.453) (4.724:4.724:4.724))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[50\]_SE.I (7.364:7.364:7.364) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[42\]_SE.I (7.364:7.364:7.364) (4.635:4.635:4.635))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[43\]_SE.I (7.365:7.365:7.365) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[44\]_SE.I (7.365:7.365:7.365) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[45\]_SE.I (7.364:7.364:7.364) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[46\]_SE.I (7.364:7.364:7.364) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[47\]_SE.I (7.364:7.364:7.364) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[48\]_SE.I (7.364:7.364:7.364) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[49\]_SE.I (7.364:7.364:7.364) (4.636:4.636:4.636))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[40\]_SE.I (7.360:7.360:7.360) (4.631:4.631:4.631))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[39\]_SE.I (7.396:7.396:7.396) (4.667:4.667:4.667))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[55\]_SE.I (7.372:7.372:7.372) (4.643:4.643:4.643))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[41\]_SE.I (7.363:7.363:7.363) (4.635:4.635:4.635))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[51\]_SE.I (7.364:7.364:7.364) (4.635:4.635:4.635))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[52\]_SE.I (7.364:7.364:7.364) (4.635:4.635:4.635))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[54\]_SE.I (7.368:7.368:7.368) (4.640:4.640:4.640))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[38\]_SE.I (7.401:7.401:7.401) (4.673:4.673:4.673))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[5\]_SE.I (7.403:7.403:7.403) (4.674:4.674:4.674))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[4\]_SE.I (7.403:7.403:7.403) (4.674:4.674:4.674))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[3\]_SE.I (7.403:7.403:7.403) (4.675:4.675:4.675))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[2\]_SE.I (7.402:7.402:7.402) (4.674:4.674:4.674))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[0\]_SE.I (7.366:7.366:7.366) (4.637:4.637:4.637))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[1\]_SE.I (7.366:7.366:7.366) (4.637:4.637:4.637))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[53\]_SE.I (7.364:7.364:7.364) (4.635:4.635:4.635))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[11\]_SE.I (7.431:7.431:7.431) (4.703:4.703:4.703))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[34\]_SE.I (7.440:7.440:7.440) (4.712:4.712:4.712))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[10\]_SE.I (7.432:7.432:7.432) (4.703:4.703:4.703))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[35\]_SE.I (7.439:7.439:7.439) (4.711:4.711:4.711))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[13\]_SE.I (7.431:7.431:7.431) (4.702:4.702:4.702))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[12\]_SE.I (7.431:7.431:7.431) (4.702:4.702:4.702))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[37\]_SE.I (7.435:7.435:7.435) (4.706:4.706:4.706))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[36\]_SE.I (7.437:7.437:7.437) (4.709:4.709:4.709))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[7\]_SE.I (7.418:7.418:7.418) (4.689:4.689:4.689))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[8\]_SE.I (7.411:7.411:7.411) (4.682:4.682:4.682))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[9\]_SE.I (7.423:7.423:7.423) (4.695:4.695:4.695))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[6\]_SE.I (7.403:7.403:7.403) (4.674:4.674:4.674))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[60\]_SE.I (7.409:7.409:7.409) (4.680:4.680:4.680))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[61\]_SE.I (7.409:7.409:7.409) (4.680:4.680:4.680))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[62\]_SE.I (7.409:7.409:7.409) (4.681:4.681:4.681))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[63\]_SE.I (7.409:7.409:7.409) (4.681:4.681:4.681))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[64\]_SE.I (7.438:7.438:7.438) (4.709:4.709:4.709))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[65\]_SE.I (7.438:7.438:7.438) (4.709:4.709:4.709))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[66\]_SE.I (7.438:7.438:7.438) (4.709:4.709:4.709))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[67\]_SE.I (7.420:7.420:7.420) (4.691:4.691:4.691))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[58\]_SE.I (7.409:7.409:7.409) (4.680:4.680:4.680))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[59\]_SE.I (7.409:7.409:7.409) (4.680:4.680:4.680))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[56\]_SE.I (7.379:7.379:7.379) (4.651:4.651:4.651))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[68\]_SE.I (7.419:7.419:7.419) (4.691:4.691:4.691))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[69\]_SE.I (7.415:7.415:7.415) (4.686:4.686:4.686))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[57\]_SE.I (7.382:7.382:7.382) (4.654:4.654:4.654))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[31\]_SE.I (7.453:7.453:7.453) (4.724:4.724:4.724))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[32\]_SE.I (7.443:7.443:7.443) (4.714:4.714:4.714))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[28\]_SE.I (7.453:7.453:7.453) (4.724:4.724:4.724))
(INTERCONNECT io_in[3] ANTENNA_u_scanchain_local\.scan_flop\[17\]_SE.I (7.456:7.456:7.456) (4.727:4.727:4.727))
(INTERCONNECT io_in[4] _2839_.CLK (19.664:19.664:19.664) (12.460:12.460:12.460))
(INTERCONNECT io_in[4] _2829_.CLK (19.667:19.667:19.667) (12.463:12.463:12.463))
(INTERCONNECT io_in[4] u_cpu\.rf_ram\.RAM0.CLK (19.565:19.565:19.565) (12.361:12.361:12.361))
(INTERCONNECT io_in[4] _2706_.CLK (19.544:19.544:19.544) (12.341:12.341:12.341))
(INTERCONNECT io_in[4] _2799_.CLK (19.562:19.562:19.562) (12.358:12.358:12.358))
(INTERCONNECT io_in[4] _2800_.CLK (19.562:19.562:19.562) (12.359:12.359:12.359))
(INTERCONNECT io_in[4] _2707_.CLK (19.544:19.544:19.544) (12.341:12.341:12.341))
(INTERCONNECT io_in[4] _2783_.CLK (19.395:19.395:19.395) (12.192:12.192:12.192))
(INTERCONNECT io_in[4] _2683_.CLK (19.520:19.520:19.520) (12.317:12.317:12.317))
(INTERCONNECT io_in[4] _2813_.CLK (19.503:19.503:19.503) (12.299:12.299:12.299))
(INTERCONNECT io_in[4] _2659_.CLK (19.438:19.438:19.438) (12.234:12.234:12.234))
(INTERCONNECT io_in[4] _2684_.CLK (19.520:19.520:19.520) (12.317:12.317:12.317))
(INTERCONNECT io_in[4] _2685_.CLK (19.475:19.475:19.475) (12.272:12.272:12.272))
(INTERCONNECT io_in[4] _2687_.CLK (19.490:19.490:19.490) (12.287:12.287:12.287))
(INTERCONNECT io_in[4] _2663_.CLK (19.492:19.492:19.492) (12.288:12.288:12.288))
(INTERCONNECT io_in[4] _2686_.CLK (19.476:19.476:19.476) (12.273:12.273:12.273))
(INTERCONNECT io_in[4] _2750_.CLK (19.465:19.465:19.465) (12.261:12.261:12.261))
(INTERCONNECT io_in[4] _2751_.CLK (19.484:19.484:19.484) (12.280:12.280:12.280))
(INTERCONNECT io_in[4] _2660_.CLK (19.498:19.498:19.498) (12.295:12.295:12.295))
(INTERCONNECT io_in[4] _2662_.CLK (19.498:19.498:19.498) (12.294:12.294:12.294))
(INTERCONNECT io_in[4] _2664_.CLK (19.506:19.506:19.506) (12.303:12.303:12.303))
(INTERCONNECT io_in[4] _2786_.CLK (19.395:19.395:19.395) (12.192:12.192:12.192))
(INTERCONNECT io_in[4] _2784_.CLK (19.395:19.395:19.395) (12.192:12.192:12.192))
(INTERCONNECT io_in[4] _2748_.CLK (19.447:19.447:19.447) (12.244:12.244:12.244))
(INTERCONNECT io_in[4] _2747_.CLK (19.441:19.441:19.441) (12.238:12.238:12.238))
(INTERCONNECT io_in[4] _2746_.CLK (19.430:19.430:19.430) (12.226:12.226:12.226))
(INTERCONNECT io_in[4] _2745_.CLK (19.423:19.423:19.423) (12.220:12.220:12.220))
(INTERCONNECT io_in[4] _2749_.CLK (19.454:19.454:19.454) (12.251:12.251:12.251))
(INTERCONNECT io_in[4] _2744_.CLK (19.340:19.340:19.340) (12.136:12.136:12.136))
(INTERCONNECT io_in[4] _2785_.CLK (19.395:19.395:19.395) (12.192:12.192:12.192))
(INTERCONNECT io_in[4] _2788_.CLK (19.438:19.438:19.438) (12.234:12.234:12.234))
(INTERCONNECT io_in[4] _2779_.CLK (19.405:19.405:19.405) (12.201:12.201:12.201))
(INTERCONNECT io_in[4] _2742_.CLK (19.340:19.340:19.340) (12.136:12.136:12.136))
(INTERCONNECT io_in[4] _2782_.CLK (19.413:19.413:19.413) (12.210:12.210:12.210))
(INTERCONNECT io_in[4] _2743_.CLK (19.340:19.340:19.340) (12.136:12.136:12.136))
(INTERCONNECT io_in[4] _2781_.CLK (19.395:19.395:19.395) (12.192:12.192:12.192))
(INTERCONNECT io_in[4] _2787_.CLK (19.395:19.395:19.395) (12.192:12.192:12.192))
(INTERCONNECT io_in[4] _2780_.CLK (19.394:19.394:19.394) (12.191:12.191:12.191))
(INTERCONNECT io_in[4] _2741_.CLK (19.358:19.358:19.358) (12.155:12.155:12.155))
(INTERCONNECT io_in[4] _2777_.CLK (19.423:19.423:19.423) (12.220:12.220:12.220))
(INTERCONNECT io_in[4] _2774_.CLK (19.464:19.464:19.464) (12.260:12.260:12.260))
(INTERCONNECT io_in[4] _2775_.CLK (19.442:19.442:19.442) (12.239:12.239:12.239))
(INTERCONNECT io_in[4] _2776_.CLK (19.428:19.428:19.428) (12.225:12.225:12.225))
(INTERCONNECT io_in[4] _2740_.CLK (19.395:19.395:19.395) (12.192:12.192:12.192))
(INTERCONNECT io_in[4] _2739_.CLK (19.445:19.445:19.445) (12.241:12.241:12.241))
(INTERCONNECT io_in[4] _2738_.CLK (19.466:19.466:19.466) (12.263:12.263:12.263))
(INTERCONNECT io_in[4] _2778_.CLK (19.414:19.414:19.414) (12.210:12.210:12.210))
(INTERCONNECT io_in[4] _2789_.CLK (19.437:19.437:19.437) (12.234:12.234:12.234))
(INTERCONNECT io_in[4] _2737_.CLK (19.298:19.298:19.298) (12.095:12.095:12.095))
(INTERCONNECT io_in[4] _2760_.CLK (19.463:19.463:19.463) (12.260:12.260:12.260))
(INTERCONNECT io_in[4] _2798_.CLK (19.471:19.471:19.471) (12.267:12.267:12.267))
(INTERCONNECT io_in[4] _2709_.CLK (19.504:19.504:19.504) (12.301:12.301:12.301))
(INTERCONNECT io_in[4] _2812_.CLK (19.504:19.504:19.504) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] _2810_.CLK (19.504:19.504:19.504) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] _2656_.CLK (19.436:19.436:19.436) (12.233:12.233:12.233))
(INTERCONNECT io_in[4] _2658_.CLK (19.436:19.436:19.436) (12.233:12.233:12.233))
(INTERCONNECT io_in[4] _2657_.CLK (19.436:19.436:19.436) (12.233:12.233:12.233))
(INTERCONNECT io_in[4] _2752_.CLK (19.484:19.484:19.484) (12.281:12.281:12.281))
(INTERCONNECT io_in[4] _2661_.CLK (19.503:19.503:19.503) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] _2708_.CLK (19.504:19.504:19.504) (12.301:12.301:12.301))
(INTERCONNECT io_in[4] _2759_.CLK (19.471:19.471:19.471) (12.267:12.267:12.267))
(INTERCONNECT io_in[4] _2710_.CLK (19.505:19.505:19.505) (12.301:12.301:12.301))
(INTERCONNECT io_in[4] _2677_.CLK (19.521:19.521:19.521) (12.317:12.317:12.317))
(INTERCONNECT io_in[4] _2671_.CLK (19.555:19.555:19.555) (12.351:12.351:12.351))
(INTERCONNECT io_in[4] _2673_.CLK (19.555:19.555:19.555) (12.351:12.351:12.351))
(INTERCONNECT io_in[4] _2805_.CLK (19.554:19.554:19.554) (12.350:12.350:12.350))
(INTERCONNECT io_in[4] _2804_.CLK (19.547:19.547:19.547) (12.344:12.344:12.344))
(INTERCONNECT io_in[4] _2803_.CLK (19.548:19.548:19.548) (12.345:12.345:12.345))
(INTERCONNECT io_in[4] _2802_.CLK (19.555:19.555:19.555) (12.352:12.352:12.352))
(INTERCONNECT io_in[4] _2670_.CLK (19.554:19.554:19.554) (12.351:12.351:12.351))
(INTERCONNECT io_in[4] _2676_.CLK (19.521:19.521:19.521) (12.317:12.317:12.317))
(INTERCONNECT io_in[4] _2675_.CLK (19.555:19.555:19.555) (12.351:12.351:12.351))
(INTERCONNECT io_in[4] _2674_.CLK (19.555:19.555:19.555) (12.351:12.351:12.351))
(INTERCONNECT io_in[4] _2669_.CLK (19.554:19.554:19.554) (12.350:12.350:12.350))
(INTERCONNECT io_in[4] _2801_.CLK (19.554:19.554:19.554) (12.350:12.350:12.350))
(INTERCONNECT io_in[4] _2680_.CLK (19.522:19.522:19.522) (12.318:12.318:12.318))
(INTERCONNECT io_in[4] _2682_.CLK (19.520:19.520:19.520) (12.316:12.316:12.316))
(INTERCONNECT io_in[4] _2678_.CLK (19.521:19.521:19.521) (12.317:12.317:12.317))
(INTERCONNECT io_in[4] _2679_.CLK (19.521:19.521:19.521) (12.317:12.317:12.317))
(INTERCONNECT io_in[4] _2666_.CLK (19.521:19.521:19.521) (12.318:12.318:12.318))
(INTERCONNECT io_in[4] _2681_.CLK (19.520:19.520:19.520) (12.316:12.316:12.316))
(INTERCONNECT io_in[4] _2672_.CLK (19.528:19.528:19.528) (12.325:12.325:12.325))
(INTERCONNECT io_in[4] _2807_.CLK (19.543:19.543:19.543) (12.340:12.340:12.340))
(INTERCONNECT io_in[4] _2806_.CLK (19.547:19.547:19.547) (12.344:12.344:12.344))
(INTERCONNECT io_in[4] _2668_.CLK (19.528:19.528:19.528) (12.324:12.324:12.324))
(INTERCONNECT io_in[4] _2811_.CLK (19.532:19.532:19.532) (12.329:12.329:12.329))
(INTERCONNECT io_in[4] _2814_.CLK (19.512:19.512:19.512) (12.309:12.309:12.309))
(INTERCONNECT io_in[4] _2667_.CLK (19.528:19.528:19.528) (12.324:12.324:12.324))
(INTERCONNECT io_in[4] _2809_.CLK (19.538:19.538:19.538) (12.334:12.334:12.334))
(INTERCONNECT io_in[4] _2808_.CLK (19.512:19.512:19.512) (12.308:12.308:12.308))
(INTERCONNECT io_in[4] _2665_.CLK (19.514:19.514:19.514) (12.310:12.310:12.310))
(INTERCONNECT io_in[4] _2765_.CLK (19.504:19.504:19.504) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] _2764_.CLK (19.503:19.503:19.503) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] _2770_.CLK (19.470:19.470:19.470) (12.266:12.266:12.266))
(INTERCONNECT io_in[4] _2725_.CLK (19.470:19.470:19.470) (12.266:12.266:12.266))
(INTERCONNECT io_in[4] _2769_.CLK (19.469:19.469:19.469) (12.265:12.265:12.265))
(INTERCONNECT io_in[4] _2734_.CLK (19.468:19.468:19.468) (12.265:12.265:12.265))
(INTERCONNECT io_in[4] _2763_.CLK (19.503:19.503:19.503) (12.299:12.299:12.299))
(INTERCONNECT io_in[4] _2773_.CLK (19.466:19.466:19.466) (12.262:12.262:12.262))
(INTERCONNECT io_in[4] _2772_.CLK (19.466:19.466:19.466) (12.262:12.262:12.262))
(INTERCONNECT io_in[4] _2771_.CLK (19.468:19.468:19.468) (12.265:12.265:12.265))
(INTERCONNECT io_in[4] _2736_.CLK (19.467:19.467:19.467) (12.264:12.264:12.264))
(INTERCONNECT io_in[4] _2735_.CLK (19.469:19.469:19.469) (12.265:12.265:12.265))
(INTERCONNECT io_in[4] _2761_.CLK (19.479:19.479:19.479) (12.275:12.275:12.275))
(INTERCONNECT io_in[4] _2724_.CLK (19.470:19.470:19.470) (12.266:12.266:12.266))
(INTERCONNECT io_in[4] _2693_.CLK (19.544:19.544:19.544) (12.340:12.340:12.340))
(INTERCONNECT io_in[4] _2756_.CLK (19.496:19.496:19.496) (12.292:12.292:12.292))
(INTERCONNECT io_in[4] _2755_.CLK (19.503:19.503:19.503) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] _2790_.CLK (19.491:19.491:19.491) (12.288:12.288:12.288))
(INTERCONNECT io_in[4] _2757_.CLK (19.504:19.504:19.504) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] _2758_.CLK (19.504:19.504:19.504) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] _2754_.CLK (19.512:19.512:19.512) (12.309:12.309:12.309))
(INTERCONNECT io_in[4] _2652_.CLK (19.533:19.533:19.533) (12.330:12.330:12.330))
(INTERCONNECT io_in[4] _2797_.CLK (19.505:19.505:19.505) (12.301:12.301:12.301))
(INTERCONNECT io_in[4] _2823_.CLK (19.505:19.505:19.505) (12.301:12.301:12.301))
(INTERCONNECT io_in[4] _2762_.CLK (19.502:19.502:19.502) (12.299:12.299:12.299))
(INTERCONNECT io_in[4] _2753_.CLK (19.484:19.484:19.484) (12.281:12.281:12.281))
(INTERCONNECT io_in[4] _2767_.CLK (19.730:19.730:19.730) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] _2766_.CLK (19.730:19.730:19.730) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] _2768_.CLK (19.730:19.730:19.730) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] _2726_.CLK (19.731:19.731:19.731) (12.527:12.527:12.527))
(INTERCONNECT io_in[4] _2733_.CLK (19.730:19.730:19.730) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] _2732_.CLK (19.730:19.730:19.730) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] _2731_.CLK (19.730:19.730:19.730) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] _2730_.CLK (19.730:19.730:19.730) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] _2729_.CLK (19.730:19.730:19.730) (12.525:12.525:12.525))
(INTERCONNECT io_in[4] _2728_.CLK (19.730:19.730:19.730) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] _2727_.CLK (19.731:19.731:19.731) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] _2722_.CLK (19.731:19.731:19.731) (12.527:12.527:12.527))
(INTERCONNECT io_in[4] _2655_.CLK (19.731:19.731:19.731) (12.527:12.527:12.527))
(INTERCONNECT io_in[4] _2834_.CLK (19.731:19.731:19.731) (12.527:12.527:12.527))
(INTERCONNECT io_in[4] _2824_.CLK (19.724:19.724:19.724) (12.520:12.520:12.520))
(INTERCONNECT io_in[4] _2723_.CLK (19.713:19.713:19.713) (12.509:12.509:12.509))
(INTERCONNECT io_in[4] _2653_.CLK (19.731:19.731:19.731) (12.527:12.527:12.527))
(INTERCONNECT io_in[4] _2651_.CLK (19.731:19.731:19.731) (12.527:12.527:12.527))
(INTERCONNECT io_in[4] _2821_.CLK (19.713:19.713:19.713) (12.509:12.509:12.509))
(INTERCONNECT io_in[4] _2643_.CLK (19.504:19.504:19.504) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] _2649_.CLK (19.715:19.715:19.715) (12.511:12.511:12.511))
(INTERCONNECT io_in[4] _2646_.CLK (19.715:19.715:19.715) (12.510:12.510:12.510))
(INTERCONNECT io_in[4] _2625_.CLK (19.717:19.717:19.717) (12.513:12.513:12.513))
(INTERCONNECT io_in[4] _2845_.CLK (19.723:19.723:19.723) (12.519:12.519:12.519))
(INTERCONNECT io_in[4] _2654_.CLK (19.719:19.719:19.719) (12.515:12.515:12.515))
(INTERCONNECT io_in[4] _2650_.CLK (19.715:19.715:19.715) (12.511:12.511:12.511))
(INTERCONNECT io_in[4] _2648_.CLK (19.729:19.729:19.729) (12.524:12.524:12.524))
(INTERCONNECT io_in[4] _2645_.CLK (19.713:19.713:19.713) (12.509:12.509:12.509))
(INTERCONNECT io_in[4] _2644_.CLK (19.713:19.713:19.713) (12.509:12.509:12.509))
(INTERCONNECT io_in[4] _2647_.CLK (19.724:19.724:19.724) (12.520:12.520:12.520))
(INTERCONNECT io_in[4] _2721_.CLK (19.581:19.581:19.581) (12.378:12.378:12.378))
(INTERCONNECT io_in[4] _2705_.CLK (19.544:19.544:19.544) (12.340:12.340:12.340))
(INTERCONNECT io_in[4] _2692_.CLK (19.581:19.581:19.581) (12.377:12.377:12.377))
(INTERCONNECT io_in[4] _2689_.CLK (19.581:19.581:19.581) (12.378:12.378:12.378))
(INTERCONNECT io_in[4] _2688_.CLK (19.581:19.581:19.581) (12.377:12.377:12.377))
(INTERCONNECT io_in[4] _2694_.CLK (19.545:19.545:19.545) (12.341:12.341:12.341))
(INTERCONNECT io_in[4] _2714_.CLK (19.614:19.614:19.614) (12.410:12.410:12.410))
(INTERCONNECT io_in[4] _2713_.CLK (19.614:19.614:19.614) (12.410:12.410:12.410))
(INTERCONNECT io_in[4] _2690_.CLK (19.582:19.582:19.582) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] _2711_.CLK (19.581:19.581:19.581) (12.377:12.377:12.377))
(INTERCONNECT io_in[4] _2715_.CLK (19.610:19.610:19.610) (12.406:12.406:12.406))
(INTERCONNECT io_in[4] _2699_.CLK (19.602:19.602:19.602) (12.398:12.398:12.398))
(INTERCONNECT io_in[4] _2695_.CLK (19.580:19.580:19.580) (12.376:12.376:12.376))
(INTERCONNECT io_in[4] _2691_.CLK (19.579:19.579:19.579) (12.375:12.375:12.375))
(INTERCONNECT io_in[4] _2712_.CLK (19.582:19.582:19.582) (12.378:12.378:12.378))
(INTERCONNECT io_in[4] _2698_.CLK (19.649:19.649:19.649) (12.445:12.445:12.445))
(INTERCONNECT io_in[4] _2794_.CLK (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] _2719_.CLK (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] _2718_.CLK (19.647:19.647:19.647) (12.443:12.443:12.443))
(INTERCONNECT io_in[4] _2720_.CLK (19.583:19.583:19.583) (12.380:12.380:12.380))
(INTERCONNECT io_in[4] _2704_.CLK (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] _2703_.CLK (19.630:19.630:19.630) (12.426:12.426:12.426))
(INTERCONNECT io_in[4] _2795_.CLK (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] _2793_.CLK (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] _2717_.CLK (19.637:19.637:19.637) (12.434:12.434:12.434))
(INTERCONNECT io_in[4] _2716_.CLK (19.617:19.617:19.617) (12.413:12.413:12.413))
(INTERCONNECT io_in[4] _2701_.CLK (19.604:19.604:19.604) (12.400:12.400:12.400))
(INTERCONNECT io_in[4] _2700_.CLK (19.615:19.615:19.615) (12.411:12.411:12.411))
(INTERCONNECT io_in[4] _2796_.CLK (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] _2792_.CLK (19.614:19.614:19.614) (12.410:12.410:12.410))
(INTERCONNECT io_in[4] _2702_.CLK (19.639:19.639:19.639) (12.435:12.435:12.435))
(INTERCONNECT io_in[4] _2636_.CLK (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] _2842_.CLK (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] _2854_.CLK (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] _2857_.CLK (19.608:19.608:19.608) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] _2831_.CLK (19.673:19.673:19.673) (12.469:12.469:12.469))
(INTERCONNECT io_in[4] _2832_.CLK (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] _2840_.CLK (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] _2853_.CLK (19.662:19.662:19.662) (12.459:12.459:12.459))
(INTERCONNECT io_in[4] _2697_.CLK (19.608:19.608:19.608) (12.404:12.404:12.404))
(INTERCONNECT io_in[4] _2696_.CLK (19.608:19.608:19.608) (12.404:12.404:12.404))
(INTERCONNECT io_in[4] _2820_.CLK (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] _2855_.CLK (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] _2791_.CLK (19.578:19.578:19.578) (12.375:12.375:12.375))
(INTERCONNECT io_in[4] _2822_.CLK (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] _2856_.CLK (19.689:19.689:19.689) (12.485:12.485:12.485))
(INTERCONNECT io_in[4] _2847_.CLK (19.705:19.705:19.705) (12.501:12.501:12.501))
(INTERCONNECT io_in[4] _2818_.CLK (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] _2819_.CLK (19.705:19.705:19.705) (12.501:12.501:12.501))
(INTERCONNECT io_in[4] _2817_.CLK (19.705:19.705:19.705) (12.501:12.501:12.501))
(INTERCONNECT io_in[4] _2816_.CLK (19.710:19.710:19.710) (12.506:12.506:12.506))
(INTERCONNECT io_in[4] _2815_.CLK (19.706:19.706:19.706) (12.502:12.502:12.502))
(INTERCONNECT io_in[4] _2626_.CLK (19.703:19.703:19.703) (12.499:12.499:12.499))
(INTERCONNECT io_in[4] _2628_.CLK (19.705:19.705:19.705) (12.501:12.501:12.501))
(INTERCONNECT io_in[4] _2627_.CLK (19.699:19.699:19.699) (12.495:12.495:12.495))
(INTERCONNECT io_in[4] _2833_.CLK (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] _2841_.CLK (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] _2641_.CLK (19.677:19.677:19.677) (12.473:12.473:12.473))
(INTERCONNECT io_in[4] _2634_.CLK (19.677:19.677:19.677) (12.473:12.473:12.473))
(INTERCONNECT io_in[4] _2638_.CLK (19.664:19.664:19.664) (12.460:12.460:12.460))
(INTERCONNECT io_in[4] _2631_.CLK (19.677:19.677:19.677) (12.473:12.473:12.473))
(INTERCONNECT io_in[4] _2830_.CLK (19.663:19.663:19.663) (12.459:12.459:12.459))
(INTERCONNECT io_in[4] _2844_.CLK (19.687:19.687:19.687) (12.483:12.483:12.483))
(INTERCONNECT io_in[4] _2843_.CLK (19.692:19.692:19.692) (12.488:12.488:12.488))
(INTERCONNECT io_in[4] _2825_.CLK (19.691:19.691:19.691) (12.487:12.487:12.487))
(INTERCONNECT io_in[4] _2629_.CLK (19.695:19.695:19.695) (12.491:12.491:12.491))
(INTERCONNECT io_in[4] _2846_.CLK (19.687:19.687:19.687) (12.483:12.483:12.483))
(INTERCONNECT io_in[4] _2630_.CLK (19.677:19.677:19.677) (12.473:12.473:12.473))
(INTERCONNECT io_in[4] _2642_.CLK (19.687:19.687:19.687) (12.483:12.483:12.483))
(INTERCONNECT io_in[4] _2637_.CLK (19.675:19.675:19.675) (12.471:12.471:12.471))
(INTERCONNECT io_in[4] _2635_.CLK (19.687:19.687:19.687) (12.483:12.483:12.483))
(INTERCONNECT io_in[4] _2852_.CLK (19.669:19.669:19.669) (12.465:12.465:12.465))
(INTERCONNECT io_in[4] _2639_.CLK (19.667:19.667:19.667) (12.463:12.463:12.463))
(INTERCONNECT io_in[4] _2632_.CLK (19.667:19.667:19.667) (12.463:12.463:12.463))
(INTERCONNECT io_in[4] _2640_.CLK (19.667:19.667:19.667) (12.463:12.463:12.463))
(INTERCONNECT io_in[4] _2633_.CLK (19.667:19.667:19.667) (12.463:12.463:12.463))
(INTERCONNECT io_in[4] _2828_.CLK (19.670:19.670:19.670) (12.466:12.466:12.466))
(INTERCONNECT io_in[4] _2827_.CLK (19.671:19.671:19.671) (12.467:12.467:12.467))
(INTERCONNECT io_in[4] _2826_.CLK (19.671:19.671:19.671) (12.467:12.467:12.467))
(INTERCONNECT io_in[4] _2851_.CLK (19.673:19.673:19.673) (12.469:12.469:12.469))
(INTERCONNECT io_in[4] _2838_.CLK (19.673:19.673:19.673) (12.469:12.469:12.469))
(INTERCONNECT io_in[4] _2850_.CLK (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] _2849_.CLK (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] _2848_.CLK (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] _2837_.CLK (19.673:19.673:19.673) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] _2836_.CLK (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] _2835_.CLK (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] ANTENNA__2835__CLK.I (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] ANTENNA__2836__CLK.I (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] ANTENNA__2837__CLK.I (19.673:19.673:19.673) (12.469:12.469:12.469))
(INTERCONNECT io_in[4] ANTENNA__2848__CLK.I (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] ANTENNA__2849__CLK.I (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] ANTENNA__2850__CLK.I (19.674:19.674:19.674) (12.470:12.470:12.470))
(INTERCONNECT io_in[4] ANTENNA__2838__CLK.I (19.672:19.672:19.672) (12.468:12.468:12.468))
(INTERCONNECT io_in[4] ANTENNA__2851__CLK.I (19.673:19.673:19.673) (12.469:12.469:12.469))
(INTERCONNECT io_in[4] ANTENNA__2826__CLK.I (19.671:19.671:19.671) (12.467:12.467:12.467))
(INTERCONNECT io_in[4] ANTENNA__2827__CLK.I (19.671:19.671:19.671) (12.467:12.467:12.467))
(INTERCONNECT io_in[4] ANTENNA__2828__CLK.I (19.670:19.670:19.670) (12.466:12.466:12.466))
(INTERCONNECT io_in[4] ANTENNA__2633__CLK.I (19.667:19.667:19.667) (12.463:12.463:12.463))
(INTERCONNECT io_in[4] ANTENNA__2640__CLK.I (19.667:19.667:19.667) (12.463:12.463:12.463))
(INTERCONNECT io_in[4] ANTENNA__2632__CLK.I (19.677:19.677:19.677) (12.473:12.473:12.473))
(INTERCONNECT io_in[4] ANTENNA__2639__CLK.I (19.664:19.664:19.664) (12.460:12.460:12.460))
(INTERCONNECT io_in[4] ANTENNA__2852__CLK.I (19.667:19.667:19.667) (12.464:12.464:12.464))
(INTERCONNECT io_in[4] ANTENNA__2635__CLK.I (19.687:19.687:19.687) (12.483:12.483:12.483))
(INTERCONNECT io_in[4] ANTENNA__2637__CLK.I (19.686:19.686:19.686) (12.482:12.482:12.482))
(INTERCONNECT io_in[4] ANTENNA__2642__CLK.I (19.687:19.687:19.687) (12.483:12.483:12.483))
(INTERCONNECT io_in[4] ANTENNA__2630__CLK.I (19.681:19.681:19.681) (12.477:12.477:12.477))
(INTERCONNECT io_in[4] ANTENNA__2846__CLK.I (19.687:19.687:19.687) (12.483:12.483:12.483))
(INTERCONNECT io_in[4] ANTENNA__2629__CLK.I (19.697:19.697:19.697) (12.493:12.493:12.493))
(INTERCONNECT io_in[4] ANTENNA__2825__CLK.I (19.695:19.695:19.695) (12.491:12.491:12.491))
(INTERCONNECT io_in[4] ANTENNA__2843__CLK.I (19.692:19.692:19.692) (12.488:12.488:12.488))
(INTERCONNECT io_in[4] ANTENNA__2844__CLK.I (19.689:19.689:19.689) (12.485:12.485:12.485))
(INTERCONNECT io_in[4] ANTENNA__2830__CLK.I (19.670:19.670:19.670) (12.466:12.466:12.466))
(INTERCONNECT io_in[4] ANTENNA__2631__CLK.I (19.677:19.677:19.677) (12.473:12.473:12.473))
(INTERCONNECT io_in[4] ANTENNA__2638__CLK.I (19.666:19.666:19.666) (12.462:12.462:12.462))
(INTERCONNECT io_in[4] ANTENNA__2634__CLK.I (19.677:19.677:19.677) (12.473:12.473:12.473))
(INTERCONNECT io_in[4] ANTENNA__2641__CLK.I (19.677:19.677:19.677) (12.473:12.473:12.473))
(INTERCONNECT io_in[4] ANTENNA__2841__CLK.I (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] ANTENNA__2833__CLK.I (19.689:19.689:19.689) (12.485:12.485:12.485))
(INTERCONNECT io_in[4] ANTENNA__2627__CLK.I (19.702:19.702:19.702) (12.497:12.497:12.497))
(INTERCONNECT io_in[4] ANTENNA__2628__CLK.I (19.705:19.705:19.705) (12.501:12.501:12.501))
(INTERCONNECT io_in[4] ANTENNA__2626__CLK.I (19.703:19.703:19.703) (12.499:12.499:12.499))
(INTERCONNECT io_in[4] ANTENNA__2815__CLK.I (19.713:19.713:19.713) (12.509:12.509:12.509))
(INTERCONNECT io_in[4] ANTENNA__2816__CLK.I (19.713:19.713:19.713) (12.509:12.509:12.509))
(INTERCONNECT io_in[4] ANTENNA__2817__CLK.I (19.707:19.707:19.707) (12.503:12.503:12.503))
(INTERCONNECT io_in[4] ANTENNA__2819__CLK.I (19.708:19.708:19.708) (12.504:12.504:12.504))
(INTERCONNECT io_in[4] ANTENNA__2818__CLK.I (19.705:19.705:19.705) (12.501:12.501:12.501))
(INTERCONNECT io_in[4] ANTENNA__2847__CLK.I (19.706:19.706:19.706) (12.501:12.501:12.501))
(INTERCONNECT io_in[4] ANTENNA__2856__CLK.I (19.700:19.700:19.700) (12.496:12.496:12.496))
(INTERCONNECT io_in[4] ANTENNA__2822__CLK.I (19.713:19.713:19.713) (12.509:12.509:12.509))
(INTERCONNECT io_in[4] ANTENNA__2791__CLK.I (19.709:19.709:19.709) (12.505:12.505:12.505))
(INTERCONNECT io_in[4] ANTENNA__2855__CLK.I (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] ANTENNA__2820__CLK.I (19.700:19.700:19.700) (12.496:12.496:12.496))
(INTERCONNECT io_in[4] ANTENNA__2696__CLK.I (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] ANTENNA__2697__CLK.I (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] ANTENNA__2853__CLK.I (19.654:19.654:19.654) (12.450:12.450:12.450))
(INTERCONNECT io_in[4] ANTENNA__2840__CLK.I (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] ANTENNA__2832__CLK.I (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] ANTENNA__2831__CLK.I (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] ANTENNA__2857__CLK.I (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] ANTENNA__2854__CLK.I (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] ANTENNA__2842__CLK.I (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] ANTENNA__2636__CLK.I (19.700:19.700:19.700) (12.496:12.496:12.496))
(INTERCONNECT io_in[4] ANTENNA__2702__CLK.I (19.647:19.647:19.647) (12.444:12.444:12.444))
(INTERCONNECT io_in[4] ANTENNA__2792__CLK.I (19.607:19.607:19.607) (12.404:12.404:12.404))
(INTERCONNECT io_in[4] ANTENNA__2796__CLK.I (19.607:19.607:19.607) (12.403:12.403:12.403))
(INTERCONNECT io_in[4] ANTENNA__2700__CLK.I (19.569:19.569:19.569) (12.366:12.366:12.366))
(INTERCONNECT io_in[4] ANTENNA__2701__CLK.I (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] ANTENNA__2716__CLK.I (19.608:19.608:19.608) (12.404:12.404:12.404))
(INTERCONNECT io_in[4] ANTENNA__2717__CLK.I (19.643:19.643:19.643) (12.440:12.440:12.440))
(INTERCONNECT io_in[4] ANTENNA__2793__CLK.I (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] ANTENNA__2795__CLK.I (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] ANTENNA__2703__CLK.I (19.602:19.602:19.602) (12.399:12.399:12.399))
(INTERCONNECT io_in[4] ANTENNA__2704__CLK.I (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] ANTENNA__2720__CLK.I (19.622:19.622:19.622) (12.418:12.418:12.418))
(INTERCONNECT io_in[4] ANTENNA__2718__CLK.I (19.642:19.642:19.642) (12.438:12.438:12.438))
(INTERCONNECT io_in[4] ANTENNA__2719__CLK.I (19.583:19.583:19.583) (12.380:12.380:12.380))
(INTERCONNECT io_in[4] ANTENNA__2794__CLK.I (19.583:19.583:19.583) (12.379:12.379:12.379))
(INTERCONNECT io_in[4] ANTENNA__2698__CLK.I (19.684:19.684:19.684) (12.480:12.480:12.480))
(INTERCONNECT io_in[4] ANTENNA__2712__CLK.I (19.549:19.549:19.549) (12.346:12.346:12.346))
(INTERCONNECT io_in[4] ANTENNA__2691__CLK.I (19.713:19.713:19.713) (12.509:12.509:12.509))
(INTERCONNECT io_in[4] ANTENNA__2695__CLK.I (19.713:19.713:19.713) (12.509:12.509:12.509))
(INTERCONNECT io_in[4] ANTENNA__2699__CLK.I (19.609:19.609:19.609) (12.405:12.405:12.405))
(INTERCONNECT io_in[4] ANTENNA__2715__CLK.I (19.560:19.560:19.560) (12.356:12.356:12.356))
(INTERCONNECT io_in[4] ANTENNA__2711__CLK.I (19.528:19.528:19.528) (12.324:12.324:12.324))
(INTERCONNECT io_in[4] ANTENNA__2690__CLK.I (19.596:19.596:19.596) (12.392:12.392:12.392))
(INTERCONNECT io_in[4] ANTENNA__2713__CLK.I (19.592:19.592:19.592) (12.388:12.388:12.388))
(INTERCONNECT io_in[4] ANTENNA__2714__CLK.I (19.586:19.586:19.586) (12.382:12.382:12.382))
(INTERCONNECT io_in[4] ANTENNA__2694__CLK.I (19.504:19.504:19.504) (12.300:12.300:12.300))
(INTERCONNECT io_in[4] ANTENNA__2688__CLK.I (19.516:19.516:19.516) (12.312:12.312:12.312))
(INTERCONNECT io_in[4] ANTENNA__2689__CLK.I (19.497:19.497:19.497) (12.293:12.293:12.293))
(INTERCONNECT io_in[4] ANTENNA__2692__CLK.I (19.516:19.516:19.516) (12.312:12.312:12.312))
(INTERCONNECT io_in[4] ANTENNA__2705__CLK.I (19.502:19.502:19.502) (12.299:12.299:12.299))
(INTERCONNECT io_in[4] ANTENNA__2721__CLK.I (19.516:19.516:19.516) (12.312:12.312:12.312))
(INTERCONNECT io_in[4] ANTENNA__2647__CLK.I (19.726:19.726:19.726) (12.522:12.522:12.522))
(INTERCONNECT io_in[4] ANTENNA__2644__CLK.I (19.716:19.716:19.716) (12.512:12.512:12.512))
(INTERCONNECT io_in[4] ANTENNA__2645__CLK.I (19.716:19.716:19.716) (12.512:12.512:12.512))
(INTERCONNECT io_in[4] ANTENNA__2648__CLK.I (19.729:19.729:19.729) (12.525:12.525:12.525))
(INTERCONNECT io_in[4] ANTENNA__2650__CLK.I (19.726:19.726:19.726) (12.522:12.522:12.522))
(INTERCONNECT io_in[4] ANTENNA__2654__CLK.I (19.721:19.721:19.721) (12.517:12.517:12.517))
(INTERCONNECT io_in[4] ANTENNA__2845__CLK.I (19.723:19.723:19.723) (12.519:12.519:12.519))
(INTERCONNECT io_in[4] ANTENNA__2625__CLK.I (19.720:19.720:19.720) (12.516:12.516:12.516))
(INTERCONNECT io_in[4] ANTENNA__2646__CLK.I (19.717:19.717:19.717) (12.513:12.513:12.513))
(INTERCONNECT io_in[4] ANTENNA__2649__CLK.I (19.726:19.726:19.726) (12.522:12.522:12.522))
(INTERCONNECT io_in[4] ANTENNA__2643__CLK.I (19.731:19.731:19.731) (12.527:12.527:12.527))
(INTERCONNECT io_in[4] ANTENNA__2821__CLK.I (19.724:19.724:19.724) (12.520:12.520:12.520))
(INTERCONNECT io_in[4] ANTENNA__2651__CLK.I (19.731:19.731:19.731) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] ANTENNA__2653__CLK.I (19.724:19.724:19.724) (12.520:12.520:12.520))
(INTERCONNECT io_in[4] ANTENNA__2723__CLK.I (19.731:19.731:19.731) (12.527:12.527:12.527))
(INTERCONNECT io_in[4] ANTENNA__2824__CLK.I (19.728:19.728:19.728) (12.523:12.523:12.523))
(INTERCONNECT io_in[4] ANTENNA__2834__CLK.I (19.730:19.730:19.730) (12.526:12.526:12.526))
(INTERCONNECT io_in[4] ANTENNA__2655__CLK.I (19.724:19.724:19.724) (12.520:12.520:12.520))
(INTERCONNECT io_in[4] ANTENNA__2722__CLK.I (19.728:19.728:19.728) (12.523:12.523:12.523))
(INTERCONNECT io_in[4] ANTENNA__2727__CLK.I (19.729:19.729:19.729) (12.525:12.525:12.525))
(INTERCONNECT io_in[4] ANTENNA__2728__CLK.I (19.729:19.729:19.729) (12.525:12.525:12.525))
(INTERCONNECT io_in[4] ANTENNA__2729__CLK.I (19.730:19.730:19.730) (12.525:12.525:12.525))
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(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[27\].CLK (0.136:0.136:0.136) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[23\].CLK (0.136:0.136:0.136) (0.135:0.135:0.135))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[22\].CLK (0.137:0.137:0.137) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[19\].CLK (0.136:0.136:0.136) (0.135:0.135:0.135))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[26\].CLK (0.136:0.136:0.136) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[25\].CLK (0.136:0.136:0.136) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[24\].CLK (0.136:0.136:0.136) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[21\].CLK (0.137:0.137:0.137) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[20\].CLK (0.137:0.137:0.137) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z u_scanchain_local\.scan_flop\[18\].CLK (0.135:0.135:0.135) (0.135:0.135:0.135))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[18\]_CLK.I (0.134:0.134:0.134) (0.134:0.134:0.134))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[20\]_CLK.I (0.136:0.136:0.136) (0.135:0.135:0.135))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[21\]_CLK.I (0.136:0.136:0.136) (0.135:0.135:0.135))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[24\]_CLK.I (0.136:0.136:0.136) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[25\]_CLK.I (0.136:0.136:0.136) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[26\]_CLK.I (0.136:0.136:0.136) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[19\]_CLK.I (0.136:0.136:0.136) (0.135:0.135:0.135))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[22\]_CLK.I (0.136:0.136:0.136) (0.136:0.136:0.136))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[23\]_CLK.I (0.134:0.134:0.134) (0.134:0.134:0.134))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[27\]_CLK.I (0.133:0.133:0.133) (0.133:0.133:0.133))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[15\]_CLK.I (0.130:0.130:0.130) (0.129:0.129:0.129))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[16\]_CLK.I (0.131:0.131:0.131) (0.131:0.131:0.131))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[29\]_CLK.I (0.132:0.132:0.132) (0.132:0.132:0.132))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[14\]_CLK.I (0.124:0.124:0.124) (0.124:0.124:0.124))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[11\]_CLK.I (0.120:0.120:0.120) (0.120:0.120:0.120))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[32\]_CLK.I (0.133:0.133:0.133) (0.132:0.132:0.132))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[38\]_CLK.I (0.072:0.072:0.072) (0.072:0.072:0.072))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[5\]_CLK.I (0.063:0.063:0.063) (0.063:0.063:0.063))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[4\]_CLK.I (0.064:0.064:0.064) (0.064:0.064:0.064))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[3\]_CLK.I (0.064:0.064:0.064) (0.063:0.063:0.063))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[2\]_CLK.I (0.063:0.063:0.063) (0.063:0.063:0.063))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[39\]_CLK.I (0.061:0.061:0.061) (0.061:0.061:0.061))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[1\]_CLK.I (0.011:0.011:0.011) (0.011:0.011:0.011))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[0\]_CLK.I (0.010:0.010:0.010) (0.010:0.010:0.010))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[41\]_CLK.I (0.032:0.032:0.032) (0.032:0.032:0.032))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[40\]_CLK.I (0.039:0.039:0.039) (0.039:0.039:0.039))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[55\]_CLK.I (0.049:0.049:0.049) (0.049:0.049:0.049))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[53\]_CLK.I (0.033:0.033:0.033) (0.033:0.033:0.033))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[54\]_CLK.I (0.039:0.039:0.039) (0.039:0.039:0.039))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[51\]_CLK.I (0.016:0.016:0.016) (0.016:0.016:0.016))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[52\]_CLK.I (0.018:0.018:0.018) (0.018:0.018:0.018))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[42\]_CLK.I (0.013:0.013:0.013) (0.013:0.013:0.013))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[43\]_CLK.I (0.010:0.010:0.010) (0.010:0.010:0.010))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[44\]_CLK.I (0.011:0.011:0.011) (0.011:0.011:0.011))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[45\]_CLK.I (0.009:0.009:0.009) (0.009:0.009:0.009))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[46\]_CLK.I (0.009:0.009:0.009) (0.009:0.009:0.009))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[47\]_CLK.I (0.009:0.009:0.009) (0.009:0.009:0.009))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[48\]_CLK.I (0.009:0.009:0.009) (0.009:0.009:0.009))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[49\]_CLK.I (0.009:0.009:0.009) (0.009:0.009:0.009))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[50\]_CLK.I (0.009:0.009:0.009) (0.009:0.009:0.009))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[13\]_CLK.I (0.122:0.122:0.122) (0.122:0.122:0.122))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[12\]_CLK.I (0.123:0.123:0.123) (0.123:0.123:0.123))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[10\]_CLK.I (0.119:0.119:0.119) (0.118:0.118:0.118))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[35\]_CLK.I (0.134:0.134:0.134) (0.134:0.134:0.134))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[36\]_CLK.I (0.134:0.134:0.134) (0.134:0.134:0.134))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[37\]_CLK.I (0.127:0.127:0.127) (0.127:0.127:0.127))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[66\]_CLK.I (0.134:0.134:0.134) (0.134:0.134:0.134))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[65\]_CLK.I (0.098:0.098:0.098) (0.098:0.098:0.098))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[8\]_CLK.I (0.110:0.110:0.110) (0.109:0.109:0.109))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[7\]_CLK.I (0.110:0.110:0.110) (0.109:0.109:0.109))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[6\]_CLK.I (0.084:0.084:0.084) (0.084:0.084:0.084))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[9\]_CLK.I (0.110:0.110:0.110) (0.109:0.109:0.109))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[34\]_CLK.I (0.134:0.134:0.134) (0.133:0.133:0.133))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[60\]_CLK.I (0.097:0.097:0.097) (0.097:0.097:0.097))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[61\]_CLK.I (0.098:0.098:0.098) (0.097:0.097:0.097))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[67\]_CLK.I (0.107:0.107:0.107) (0.107:0.107:0.107))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[62\]_CLK.I (0.098:0.098:0.098) (0.097:0.097:0.097))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[63\]_CLK.I (0.098:0.098:0.098) (0.097:0.097:0.097))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[64\]_CLK.I (0.098:0.098:0.098) (0.098:0.098:0.098))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.out_flop_CLKN.I (0.099:0.099:0.099) (0.099:0.099:0.099))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[56\]_CLK.I (0.050:0.050:0.050) (0.050:0.050:0.050))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[57\]_CLK.I (0.097:0.097:0.097) (0.097:0.097:0.097))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[58\]_CLK.I (0.096:0.096:0.096) (0.096:0.096:0.096))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[59\]_CLK.I (0.096:0.096:0.096) (0.096:0.096:0.096))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.output_buffers\[3\]_I.I (0.097:0.097:0.097) (0.097:0.097:0.097))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[68\]_CLK.I (0.107:0.107:0.107) (0.107:0.107:0.107))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[69\]_CLK.I (0.104:0.104:0.104) (0.104:0.104:0.104))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[31\]_CLK.I (0.133:0.133:0.133) (0.132:0.132:0.132))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[30\]_CLK.I (0.130:0.130:0.130) (0.129:0.129:0.129))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[33\]_CLK.I (0.134:0.134:0.134) (0.133:0.133:0.133))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[17\]_CLK.I (0.132:0.132:0.132) (0.132:0.132:0.132))
(INTERCONNECT u_scanchain_local\.input_buf_clk.Z ANTENNA_u_scanchain_local\.scan_flop\[28\]_CLK.I (0.133:0.133:0.133) (0.132:0.132:0.132))
(INTERCONNECT u_scanchain_local\.out_flop.Q u_scanchain_local\.output_buffers\[2\].I (0.000:0.000:0.000) (0.000:0.000:0.000))
(INTERCONNECT u_scanchain_local\.output_buffers\[2\].Z _3016_.I (0.000:0.000:0.000) (0.000:0.000:0.000))
(INTERCONNECT u_scanchain_local\.output_buffers\[3\].Z _3015_.I (0.000:0.000:0.000))
(INTERCONNECT u_scanchain_local\.scan_flop\[0\].Q _2348_.A3 (0.000:0.000:0.000) (0.000:0.000:0.000))
(INTERCONNECT u_scanchain_local\.scan_flop\[0\].Q u_scanchain_local\.scan_flop\[1\].D (0.000:0.000:0.000))
(INTERCONNECT u_scanchain_local\.scan_flop\[10\].Q _1905_.A1 (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT u_scanchain_local\.scan_flop\[10\].Q _1978_.I0 (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT u_scanchain_local\.scan_flop\[10\].Q _2012_.A2 (0.002:0.002:0.002) (0.002:0.002:0.002))
(INTERCONNECT u_scanchain_local\.scan_flop\[10\].Q _2173_.I1 (0.002:0.002:0.002) (0.002:0.002:0.002))
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(CELL
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(COND A1===1'b1 && A2===1'b0
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(COND A1===1'b0 && A2===1'b1
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(CELL
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(COND A1===1'b0 && A2===1'b1
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(COND A1===1'b0 && A2===1'b0
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(CELL
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(CELL
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(SETUP (negedge D) (posedge CLK) (0.174:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (0.010:0.009:0.007))
(HOLD (negedge D) (posedge CLK) (0.055:0.057:0.058))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(IOPATH CLK Q (1.376:1.376:1.376) (1.065:1.065:1.065))
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(SETUP (negedge D) (posedge CLK) (0.081:0.081:0.081))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2631_)
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(ABSOLUTE
(IOPATH CLK Q (1.388:1.388:1.388) (1.075:1.075:1.075))
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(SETUP (negedge D) (posedge CLK) (0.086:0.086:0.086))
(HOLD (posedge D) (posedge CLK) (0.022:0.022:0.022))
(HOLD (negedge D) (posedge CLK) (0.074:0.074:0.074))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(SETUP (negedge D) (posedge CLK) (0.074:0.074:0.074))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.077:0.077:0.077))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(SETUP (negedge D) (posedge CLK) (0.083:0.083:0.083))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2634_)
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(SETUP (negedge D) (posedge CLK) (0.076:0.076:0.076))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2635_)
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(SETUP (negedge D) (posedge CLK) (0.086:0.086:0.086))
(HOLD (posedge D) (posedge CLK) (0.022:0.022:0.022))
(HOLD (negedge D) (posedge CLK) (0.074:0.074:0.074))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(INSTANCE _2636_)
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(SETUP (negedge D) (posedge CLK) (0.083:0.083:0.084))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2637_)
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(SETUP (negedge D) (posedge CLK) (0.084:0.085:0.085))
(HOLD (posedge D) (posedge CLK) (0.023:0.022:0.022))
(HOLD (negedge D) (posedge CLK) (0.074:0.074:0.074))
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(SETUP (negedge D) (posedge CLK) (0.082:0.082:0.082))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2639_)
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.396:0.396:0.396))
(SETUP (negedge D) (posedge CLK) (0.090:0.090:0.090))
(HOLD (posedge D) (posedge CLK) (0.021:0.021:0.021))
(HOLD (negedge D) (posedge CLK) (0.073:0.073:0.073))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2640_)
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(SETUP (negedge D) (posedge CLK) (0.080:0.081:0.081))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2641_)
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(SETUP (negedge D) (posedge CLK) (0.080:0.080:0.080))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
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(INSTANCE _2642_)
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(TIMINGCHECK
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(SETUP (negedge D) (posedge CLK) (0.087:0.088:0.088))
(HOLD (posedge D) (posedge CLK) (0.022:0.022:0.022))
(HOLD (negedge D) (posedge CLK) (0.074:0.074:0.074))
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(INSTANCE _2643_)
(DELAY
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.371:0.371:0.371))
(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (0.005:0.004:0.004))
(HOLD (negedge D) (posedge CLK) (0.058:0.058:0.058))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(CELL
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(INSTANCE _2644_)
(DELAY
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.373:0.378:0.382))
(SETUP (negedge D) (posedge CLK) (0.173:0.166:0.159))
(HOLD (posedge D) (posedge CLK) (-0.007:-0.039:-0.071))
(HOLD (negedge D) (posedge CLK) (0.057:0.061:0.064))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(CELL
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(INSTANCE _2645_)
(DELAY
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(IOPATH CLK Q (2.179:2.179:2.179) (1.616:1.616:1.616))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.392:0.382:0.372))
(SETUP (negedge D) (posedge CLK) (0.173:0.171:0.169))
(HOLD (posedge D) (posedge CLK) (0.009:0.005:0.002))
(HOLD (negedge D) (posedge CLK) (0.057:0.060:0.063))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2646_)
(DELAY
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(SETUP (posedge D) (posedge CLK) (0.399:0.387:0.376))
(SETUP (negedge D) (posedge CLK) (0.174:0.168:0.162))
(HOLD (posedge D) (posedge CLK) (0.010:-0.008:-0.025))
(HOLD (negedge D) (posedge CLK) (0.056:0.060:0.064))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(CELL
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(INSTANCE _2647_)
(DELAY
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(IOPATH CLK Q (1.825:1.825:1.825) (1.371:1.371:1.371))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.411:0.392:0.374))
(SETUP (negedge D) (posedge CLK) (0.164:0.169:0.173))
(HOLD (posedge D) (posedge CLK) (0.012:-0.000:-0.013))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(CELL
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(INSTANCE _2648_)
(DELAY
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(IOPATH CLK Q (1.659:1.659:1.659) (1.263:1.263:1.263))
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.407:0.407:0.407))
(SETUP (negedge D) (posedge CLK) (0.106:0.107:0.107))
(HOLD (posedge D) (posedge CLK) (0.017:0.017:0.017))
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(CELL
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(INSTANCE _2649_)
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(TIMINGCHECK
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(SETUP (negedge D) (posedge CLK) (0.174:0.168:0.162))
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(CELL
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(INSTANCE _2650_)
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(SETUP (negedge D) (posedge CLK) (0.141:0.141:0.141))
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(CELL
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(INSTANCE _2651_)
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(SETUP (negedge D) (posedge CLK) (0.161:0.167:0.174))
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(CELL
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(INSTANCE _2652_)
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(SETUP (negedge D) (posedge CLK) (0.173:0.171:0.170))
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(CELL
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(INSTANCE _2653_)
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.414:0.398:0.381))
(SETUP (negedge D) (posedge CLK) (0.158:0.166:0.173))
(HOLD (posedge D) (posedge CLK) (0.013:0.010:0.007))
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(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2654_)
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(TIMINGCHECK
(SETUP (posedge D) (posedge CLK) (0.396:0.397:0.397))
(SETUP (negedge D) (posedge CLK) (0.090:0.090:0.090))
(HOLD (posedge D) (posedge CLK) (0.021:0.021:0.021))
(HOLD (negedge D) (posedge CLK) (0.073:0.073:0.073))
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(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2655_)
(DELAY
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(SETUP (negedge D) (posedge CLK) (0.158:0.159:0.161))
(HOLD (posedge D) (posedge CLK) (0.009:-0.012:-0.033))
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(PERIOD CLK (1.107:1.107:1.107))
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(CELL
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(INSTANCE _2656_)
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(SETUP (negedge D) (posedge CLK) (0.174:0.173:0.173))
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(SETUP (negedge D) (posedge CLK) (0.174:0.164:0.155))
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(SETUP (negedge D) (posedge CLK) (0.143:0.148:0.154))
(HOLD (posedge D) (posedge CLK) (0.011:-0.038:-0.086))
(HOLD (negedge D) (posedge CLK) (0.062:0.063:0.065))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(SETUP (negedge D) (posedge CLK) (0.167:0.160:0.153))
(HOLD (posedge D) (posedge CLK) (0.010:-0.052:-0.113))
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(SETUP (negedge D) (posedge CLK) (0.152:0.153:0.154))
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(SETUP (negedge D) (posedge CLK) (0.170:0.163:0.156))
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(SETUP (negedge D) (posedge CLK) (0.157:0.157:0.156))
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(SETUP (negedge D) (posedge CLK) (0.146:0.160:0.173))
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(SETUP (negedge D) (posedge CLK) (0.131:0.152:0.173))
(HOLD (posedge D) (posedge CLK) (0.009:0.007:0.005))
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(SETUP (negedge D) (posedge CLK) (0.076:0.076:0.076))
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(SETUP (negedge D) (posedge CLK) (0.080:0.081:0.082))
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(SETUP (negedge D) (posedge CLK) (0.087:0.088:0.088))
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(INSTANCE _2727_)
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(SETUP (negedge D) (posedge CLK) (0.085:0.085:0.086))
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(PERIOD CLK (1.107:1.107:1.107))
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(SETUP (negedge D) (posedge CLK) (0.078:0.078:0.079))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
(HOLD (negedge D) (posedge CLK) (0.076:0.076:0.076))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(SETUP (negedge D) (posedge CLK) (0.090:0.090:0.091))
(HOLD (posedge D) (posedge CLK) (0.021:0.021:0.021))
(HOLD (negedge D) (posedge CLK) (0.073:0.073:0.073))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(SETUP (negedge D) (posedge CLK) (0.082:0.083:0.084))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
(HOLD (negedge D) (posedge CLK) (0.075:0.075:0.075))
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(SETUP (negedge D) (posedge CLK) (0.095:0.095:0.096))
(HOLD (posedge D) (posedge CLK) (0.020:0.020:0.020))
(HOLD (negedge D) (posedge CLK) (0.072:0.072:0.072))
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(SETUP (negedge D) (posedge CLK) (0.089:0.090:0.091))
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(SETUP (negedge D) (posedge CLK) (0.079:0.080:0.081))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
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(SETUP (negedge D) (posedge CLK) (0.079:0.079:0.080))
(HOLD (posedge D) (posedge CLK) (0.024:0.024:0.024))
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(SETUP (negedge D) (posedge CLK) (0.076:0.077:0.078))
(HOLD (posedge D) (posedge CLK) (0.025:0.025:0.025))
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(SETUP (negedge D) (posedge CLK) (0.077:0.078:0.079))
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(SETUP (negedge D) (posedge CLK) (0.084:0.084:0.085))
(HOLD (posedge D) (posedge CLK) (0.023:0.023:0.023))
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(SETUP (negedge D) (posedge CLK) (0.092:0.093:0.093))
(HOLD (posedge D) (posedge CLK) (0.020:0.020:0.020))
(HOLD (negedge D) (posedge CLK) (0.073:0.073:0.072))
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(SETUP (negedge D) (posedge CLK) (0.075:0.076:0.077))
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(SETUP (negedge D) (posedge CLK) (0.164:0.162:0.160))
(HOLD (posedge D) (posedge CLK) (0.009:-0.014:-0.036))
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(SETUP (negedge D) (posedge CLK) (0.170:0.183:0.196))
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(SETUP (negedge D) (posedge CLK) (0.134:0.175:0.216))
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(SETUP (negedge D) (posedge CLK) (0.174:0.173:0.172))
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(SETUP (negedge D) (posedge CLK) (0.139:0.156:0.172))
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(SETUP (negedge D) (posedge CLK) (0.159:0.161:0.162))
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(SETUP (negedge D) (posedge CLK) (0.075:0.125:0.174))
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(SETUP (negedge D) (posedge CLK) (0.101:0.137:0.174))
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(SETUP (negedge D) (posedge CLK) (0.093:0.133:0.174))
(HOLD (posedge D) (posedge CLK) (0.019:0.014:0.009))
(HOLD (negedge D) (posedge CLK) (0.072:0.064:0.056))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(SETUP (negedge D) (posedge CLK) (0.071:0.122:0.174))
(HOLD (posedge D) (posedge CLK) (0.022:0.016:0.010))
(HOLD (negedge D) (posedge CLK) (0.077:0.066:0.055))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(SETUP (negedge D) (posedge CLK) (0.103:0.138:0.174))
(HOLD (posedge D) (posedge CLK) (0.018:0.013:0.009))
(HOLD (negedge D) (posedge CLK) (0.070:0.063:0.056))
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(SETUP (negedge D) (posedge CLK) (0.081:0.127:0.174))
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(SETUP (negedge D) (posedge CLK) (0.089:0.131:0.174))
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(SETUP (negedge D) (posedge CLK) (0.107:0.140:0.174))
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(SETUP (negedge D) (posedge CLK) (0.094:0.134:0.174))
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(SETUP (negedge D) (posedge CLK) (0.173:0.165:0.157))
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(SETUP (negedge D) (posedge CLK) (0.173:0.170:0.167))
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(SETUP (negedge D) (posedge CLK) (0.166:0.169:0.173))
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(SETUP (negedge D) (posedge CLK) (0.174:0.168:0.162))
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(SETUP (negedge D) (posedge CLK) (0.165:0.166:0.167))
(HOLD (posedge D) (posedge CLK) (0.011:-0.013:-0.036))
(HOLD (negedge D) (posedge CLK) (0.057:0.060:0.063))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(SETUP (negedge D) (posedge CLK) (0.174:0.165:0.156))
(HOLD (posedge D) (posedge CLK) (0.008:-0.051:-0.110))
(HOLD (negedge D) (posedge CLK) (0.056:0.060:0.065))
(WIDTH (posedge CLK) (0.495:0.495:0.495))
(WIDTH (negedge CLK) (0.553:0.553:0.553))
(PERIOD CLK (1.107:1.107:1.107))
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(SETUP (negedge D) (posedge CLK) (0.174:0.174:0.173))
(HOLD (posedge D) (posedge CLK) (0.012:0.011:0.011))
(HOLD (negedge D) (posedge CLK) (0.055:0.056:0.057))
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(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
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(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
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(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
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(SETUP (negedge D) (posedge CLK) (0.170:0.170:0.171))
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(SETUP (negedge D) (posedge CLK) (0.140:0.141:0.142))
(HOLD (posedge D) (posedge CLK) (0.012:0.012:0.012))
(HOLD (negedge D) (posedge CLK) (0.062:0.062:0.062))
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(SETUP (negedge D) (posedge CLK) (0.154:0.155:0.156))
(HOLD (posedge D) (posedge CLK) (0.012:0.012:0.012))
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(SETUP (negedge D) (posedge CLK) (0.174:0.174:0.174))
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(SETUP (negedge D) (posedge CLK) (0.169:0.171:0.173))
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(SETUP (negedge D) (posedge CLK) (0.174:0.165:0.157))
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(SETUP (negedge D) (posedge CLK) (0.174:0.174:0.174))
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(INSTANCE _2836_)
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(SETUP (negedge D) (posedge CLK) (0.173:0.173:0.173))
(HOLD (posedge D) (posedge CLK) (0.005:0.005:0.005))
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(SETUP (negedge D) (posedge CLK) (0.174:0.174:0.174))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2838_)
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(SETUP (negedge D) (posedge CLK) (0.167:0.167:0.167))
(HOLD (posedge D) (posedge CLK) (-0.115:-0.115:-0.115))
(HOLD (negedge D) (posedge CLK) (0.063:0.063:0.063))
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(WIDTH (negedge CLK) (0.553:0.553:0.553))
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(INSTANCE _2839_)
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(SETUP (negedge D) (posedge CLK) (0.174:0.174:0.174))
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(INSTANCE _2840_)
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(SETUP (negedge D) (posedge CLK) (0.174:0.174:0.174))
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(SETUP (negedge D) (posedge CLK) (0.156:0.157:0.158))
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(SETUP (negedge D) (posedge CLK) (0.171:0.171:0.170))
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(SETUP (negedge D) (posedge CLK) (0.174:0.170:0.166))
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(SETUP (negedge D) (posedge CLK) (0.104:0.104:0.104))
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(SETUP (negedge D) (posedge CLK) (0.634:0.633:0.631))
(HOLD (posedge D) (posedge CLK) (-0.156:-0.156:-0.156))
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(CELL
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(INSTANCE _2847_)
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(SETUP (negedge D) (posedge CLK) (0.144:0.156:0.168))
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(SETUP (negedge D) (posedge CLK) (0.174:0.174:0.174))
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(SETUP (negedge D) (posedge CLK) (0.174:0.174:0.174))
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(COND CEN== 1'b0 && GWEN== 1'b1
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(COND CEN== 1'b0 && GWEN== 1'b1
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(HOLD (negedge D[0]) (posedge CLK) (5.907:5.907:5.907))
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(HOLD (negedge D[1]) (posedge CLK) (5.820:5.820:5.820))
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(HOLD (negedge D[2]) (posedge CLK) (5.816:5.816:5.816))
(HOLD (posedge D[3]) (posedge CLK) (4.625:4.625:4.625))
(HOLD (negedge D[3]) (posedge CLK) (5.840:5.840:5.840))
(HOLD (posedge D[4]) (posedge CLK) (4.698:4.699:4.699))
(HOLD (negedge D[4]) (posedge CLK) (5.930:5.930:5.930))
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(HOLD (negedge D[5]) (posedge CLK) (5.828:5.828:5.828))
(HOLD (posedge D[6]) (posedge CLK) (4.651:4.651:4.651))
(HOLD (negedge D[6]) (posedge CLK) (5.872:5.872:5.872))
(HOLD (posedge D[7]) (posedge CLK) (4.639:4.639:4.639))
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(SETUP (negedge D[1]) (posedge CLK) (-0.158:-0.158:-0.158))
(SETUP (posedge D[2]) (posedge CLK) (-1.694:-1.694:-1.694))
(SETUP (negedge D[2]) (posedge CLK) (-0.201:-0.201:-0.201))
(SETUP (posedge D[3]) (posedge CLK) (-1.708:-1.708:-1.708))
(SETUP (negedge D[3]) (posedge CLK) (0.000:0.000:0.000))
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(SETUP (negedge D[4]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (posedge D[5]) (posedge CLK) (-1.701:-1.701:-1.701))
(SETUP (negedge D[5]) (posedge CLK) (-0.060:-0.060:-0.060))
(SETUP (posedge D[6]) (posedge CLK) (-1.727:-1.727:-1.727))
(SETUP (negedge D[6]) (posedge CLK) (0.000:0.000:0.000))
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(HOLD (negedge A[1]) (posedge CLK) (7.886:7.886:7.886))
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(HOLD (negedge A[2]) (posedge CLK) (7.942:7.894:7.845))
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(HOLD (negedge A[3]) (posedge CLK) (7.785:7.713:7.642))
(HOLD (posedge A[4]) (posedge CLK) (7.210:7.179:7.148))
(HOLD (negedge A[4]) (posedge CLK) (7.873:7.822:7.771))
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(HOLD (negedge A[5]) (posedge CLK) (7.919:7.873:7.828))
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(HOLD (negedge A[6]) (posedge CLK) (7.883:7.833:7.784))
(HOLD (posedge A[7]) (posedge CLK) (7.606:7.508:7.409))
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(SETUP (negedge A[0]) (posedge CLK) (-1.433:-1.433:-1.433))
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(SETUP (negedge A[1]) (posedge CLK) (-1.434:-1.434:-1.434))
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(SETUP (negedge A[2]) (posedge CLK) (-1.556:-1.501:-1.446))
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(SETUP (negedge A[3]) (posedge CLK) (-1.462:-1.395:-1.328))
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(SETUP (negedge A[4]) (posedge CLK) (-1.438:-1.452:-1.466))
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(SETUP (negedge A[5]) (posedge CLK) (-1.458:-1.454:-1.450))
(SETUP (posedge A[6]) (posedge CLK) (-1.531:-1.490:-1.448))
(SETUP (negedge A[6]) (posedge CLK) (-1.435:-1.449:-1.463))
(SETUP (posedge A[7]) (posedge CLK) (-1.964:-1.837:-1.710))
(SETUP (negedge A[7]) (posedge CLK) (-1.429:-1.454:-1.478))
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(HOLD (negedge WEN[1]) (posedge CLK) (4.274:4.274:4.275))
(HOLD (posedge WEN[2]) (posedge CLK) (5.662:5.662:5.662))
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(HOLD (posedge WEN[3]) (posedge CLK) (5.662:5.662:5.662))
(HOLD (negedge WEN[3]) (posedge CLK) (4.274:4.274:4.275))
(HOLD (posedge WEN[4]) (posedge CLK) (5.662:5.662:5.662))
(HOLD (negedge WEN[4]) (posedge CLK) (4.274:4.274:4.275))
(HOLD (posedge WEN[5]) (posedge CLK) (5.662:5.662:5.662))
(HOLD (negedge WEN[5]) (posedge CLK) (4.274:4.274:4.275))
(HOLD (posedge WEN[6]) (posedge CLK) (5.662:5.662:5.662))
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(SETUP (negedge WEN[1]) (posedge CLK) (-2.312:-2.312:-2.313))
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(SETUP (negedge WEN[2]) (posedge CLK) (-2.312:-2.312:-2.313))
(SETUP (posedge WEN[3]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[3]) (posedge CLK) (-2.312:-2.312:-2.313))
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(SETUP (negedge WEN[4]) (posedge CLK) (-2.312:-2.312:-2.312))
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(SETUP (negedge WEN[5]) (posedge CLK) (-2.312:-2.312:-2.312))
(SETUP (posedge WEN[6]) (posedge CLK) (0.000:0.000:0.000))
(SETUP (negedge WEN[6]) (posedge CLK) (-2.312:-2.312:-2.312))
(SETUP (posedge WEN[7]) (posedge CLK) (0.000:0.000:0.000))
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(HOLD (posedge CEN) (posedge CLK) (11.008:11.008:11.008))
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(SETUP (negedge D) (negedge CLKN) (-0.214:-0.214:-0.214))
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(WIDTH (negedge CLKN) (0.446:0.446:0.446))
(PERIOD CLKN (1.091:1.091:1.091))
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(INSTANCE u_scanchain_local\.output_buffers\[3\])
(DELAY
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(ABSOLUTE
(IOPATH CLK Q (0.888:0.888:0.888) (0.914:0.914:0.914))
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(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.888:0.888:0.888) (0.914:0.914:0.914)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.888:0.888:0.888) (0.914:0.914:0.914)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.888:0.888:0.888) (0.914:0.914:0.914)))
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(TIMINGCHECK
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(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.386:0.414:0.441))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.551:0.547))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.386:0.414:0.441))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.454:-0.451))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.013:-0.004:-0.020))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.454:-0.451))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.003:-0.012))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.384:0.384:0.384))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.384:0.384:0.384))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.013:0.013:0.013))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.013:0.013:0.013))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[10\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.546:0.546:0.546))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.449:-0.449:-0.449))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.006:-0.006:-0.006))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.449:-0.449:-0.449))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.004:0.004:0.004))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.440))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[11\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.157:1.157:1.157) (1.098:1.098:1.098))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.157:1.157:1.157) (1.098:1.098:1.098)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.157:1.157:1.157) (1.098:1.098:1.098)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.157:1.157:1.157) (1.098:1.098:1.098)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.157:1.157:1.157) (1.098:1.098:1.098)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.539:0.539:0.539))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.477:0.477:0.477))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.477:0.477:0.477))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.434:-0.434:-0.434))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.024:-0.024:-0.024))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.434:-0.434:-0.434))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.453:-0.453:-0.453))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.453:-0.453:-0.453))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[12\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.280:1.280:1.280) (1.176:1.176:1.176))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.280:1.280:1.280) (1.176:1.176:1.176)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.280:1.280:1.280) (1.176:1.176:1.176)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.280:1.280:1.280) (1.176:1.176:1.176)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.280:1.280:1.280) (1.176:1.176:1.176)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.384:0.384:0.384))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.384:0.384:0.384))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.014:0.014:0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.409:0.409:0.409))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.000:0.000:0.000))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.000:0.000:0.000))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[13\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.430:1.430:1.430) (1.271:1.271:1.271))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.430:1.430:1.430) (1.271:1.271:1.271)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.430:1.430:1.430) (1.271:1.271:1.271)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.430:1.430:1.430) (1.271:1.271:1.271)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.430:1.430:1.430) (1.271:1.271:1.271)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.426:0.427:0.427))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.426:0.427:0.427))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.454:-0.454:-0.454))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.006:-0.006:-0.006))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.454:-0.454:-0.454))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.006:-0.006:-0.006))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[14\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.132:1.132:1.132) (1.082:1.082:1.082))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.132:1.132:1.132) (1.082:1.082:1.082)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.132:1.132:1.132) (1.082:1.082:1.082)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.132:1.132:1.132) (1.082:1.082:1.082)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.132:1.132:1.132) (1.082:1.082:1.082)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.545:0.545:0.545))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.546:0.546:0.546))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.410:0.410:0.410))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.448:-0.448:-0.448))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.448:-0.448:-0.448))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.001:0.001:0.001))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.449:0.449:0.449))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.449:0.449:0.449))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.450:-0.450:-0.450))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.450:-0.450:-0.450))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[15\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.520:1.520:1.520) (1.328:1.328:1.328))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.520:1.520:1.520) (1.328:1.328:1.328)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.520:1.520:1.520) (1.328:1.328:1.328)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.520:1.520:1.520) (1.328:1.328:1.328)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.520:1.520:1.520) (1.328:1.328:1.328)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.405:0.406:0.406))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.405:0.406:0.406))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.462:-0.462:-0.462))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.002:0.002:0.002))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.462:-0.462:-0.462))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.002:0.002:0.002))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[16\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.399:1.399:1.399) (1.252:1.252:1.252))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.399:1.399:1.399) (1.252:1.252:1.252)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.399:1.399:1.399) (1.252:1.252:1.252)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.399:1.399:1.399) (1.252:1.252:1.252)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.399:1.399:1.399) (1.252:1.252:1.252)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.462:0.462:0.462))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.462:0.462:0.462))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.449:-0.449:-0.449))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.022:-0.022:-0.022))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.449:-0.449:-0.449))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.022:-0.022:-0.022))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[17\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.376:1.376:1.376) (1.237:1.237:1.237))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.376:1.376:1.376) (1.237:1.237:1.237)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.376:1.376:1.376) (1.237:1.237:1.237)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.376:1.376:1.376) (1.237:1.237:1.237)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.376:1.376:1.376) (1.237:1.237:1.237)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.016:0.016:0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.444:0.444:0.444))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.013:-0.014:-0.014))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.013:-0.014:-0.014))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[18\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.168:1.168:1.168) (1.105:1.105:1.105))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.168:1.168:1.168) (1.105:1.105:1.105)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.168:1.168:1.168) (1.105:1.105:1.105)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.168:1.168:1.168) (1.105:1.105:1.105)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.168:1.168:1.168) (1.105:1.105:1.105)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.441))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.440:0.440:0.441))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[19\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.182:1.182:1.182) (1.114:1.114:1.114))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.182:1.182:1.182) (1.114:1.114:1.114)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.182:1.182:1.182) (1.114:1.114:1.114)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.182:1.182:1.182) (1.114:1.114:1.114)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.182:1.182:1.182) (1.114:1.114:1.114)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.387:0.387:0.387))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.387:0.387:0.387))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.012:0.012:0.012))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.000:-0.000:-0.000))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.000:-0.000:-0.000))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[1\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.570:1.570:1.570) (1.359:1.359:1.359))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.570:1.570:1.570) (1.359:1.359:1.359)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.570:1.570:1.570) (1.359:1.359:1.359)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.570:1.570:1.570) (1.359:1.359:1.359)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.570:1.570:1.570) (1.359:1.359:1.359)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.550))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.391:0.413:0.435))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.391:0.413:0.435))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.457:-0.456:-0.454))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.010:-0.004:-0.019))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.457:-0.456:-0.454))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.004:-0.011))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.464:-0.464:-0.464))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.464:-0.464:-0.464))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[20\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.126:1.126:1.126) (1.077:1.077:1.077))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.126:1.126:1.126) (1.077:1.077:1.077)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.126:1.126:1.126) (1.077:1.077:1.077)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.126:1.126:1.126) (1.077:1.077:1.077)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.126:1.126:1.126) (1.077:1.077:1.077)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.413:0.413:0.413))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.001:-0.001:-0.001))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.001:-0.001:-0.001))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[21\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.234:1.234:1.234) (1.146:1.146:1.146))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.234:1.234:1.234) (1.146:1.146:1.146)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.234:1.234:1.234) (1.146:1.146:1.146)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.234:1.234:1.234) (1.146:1.146:1.146)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.234:1.234:1.234) (1.146:1.146:1.146)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.405:0.405:0.405))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.405:0.405:0.405))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.002:0.002:0.002))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.002:0.002:0.002))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[22\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.137:1.137:1.137) (1.085:1.085:1.085))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.137:1.137:1.137) (1.085:1.085:1.085)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.137:1.137:1.137) (1.085:1.085:1.085)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.137:1.137:1.137) (1.085:1.085:1.085)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.137:1.137:1.137) (1.085:1.085:1.085)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.541:0.541:0.541))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.548:0.548:0.548))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.442:0.442:0.442))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.440:-0.440:-0.440))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.020:-0.020:-0.020))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.440:-0.440:-0.440))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.457:-0.457:-0.457))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.457:-0.457:-0.457))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.004:-0.004:-0.004))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[23\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.202:1.202:1.202) (1.126:1.126:1.126))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.202:1.202:1.202) (1.126:1.126:1.126)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.202:1.202:1.202) (1.126:1.126:1.126)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.202:1.202:1.202) (1.126:1.126:1.126)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.202:1.202:1.202) (1.126:1.126:1.126)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.384:0.384:0.384))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.384:0.384:0.384))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.014:0.014:0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.406:0.406:0.406))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.462:-0.462:-0.462))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.001:0.001:0.001))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.462:-0.462:-0.462))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.001:0.001:0.001))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[24\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.169:1.169:1.169) (1.105:1.105:1.105))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.169:1.169:1.169) (1.105:1.105:1.105)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.169:1.169:1.169) (1.105:1.105:1.105)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.169:1.169:1.169) (1.105:1.105:1.105)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.169:1.169:1.169) (1.105:1.105:1.105)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.416))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.415:0.415:0.416))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.459:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.459:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.002:-0.002:-0.002))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[25\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.120:1.120:1.120) (1.074:1.074:1.074))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.120:1.120:1.120) (1.074:1.074:1.074)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.120:1.120:1.120) (1.074:1.074:1.074)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.120:1.120:1.120) (1.074:1.074:1.074)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.120:1.120:1.120) (1.074:1.074:1.074)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.411:0.411:0.411))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.000:-0.000:-0.000))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.000:-0.000:-0.000))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[26\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.088:1.088:1.088) (1.053:1.053:1.053))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.088:1.088:1.088) (1.053:1.053:1.053)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.088:1.088:1.088) (1.053:1.053:1.053)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.088:1.088:1.088) (1.053:1.053:1.053)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.088:1.088:1.088) (1.053:1.053:1.053)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.404:0.404:0.404))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.404:0.404:0.404))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.002:0.002:0.002))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.463:-0.463:-0.463))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.002:0.002:0.002))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[27\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.160:1.160:1.160) (1.099:1.099:1.099))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.160:1.160:1.160) (1.099:1.099:1.099)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.160:1.160:1.160) (1.099:1.099:1.099)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.160:1.160:1.160) (1.099:1.099:1.099)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.160:1.160:1.160) (1.099:1.099:1.099)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.383:0.383:0.383))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.383:0.383:0.383))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.399:0.400:0.400))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.399:0.400:0.400))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.004:0.004:0.004))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.004:0.004:0.004))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[28\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.149:1.149:1.149) (1.092:1.092:1.092))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.149:1.149:1.149) (1.092:1.092:1.092)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.149:1.149:1.149) (1.092:1.092:1.092)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.149:1.149:1.149) (1.092:1.092:1.092)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.149:1.149:1.149) (1.092:1.092:1.092)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.409:0.409:0.410))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.409:0.409:0.410))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.000:0.000:0.000))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.000:0.000:0.000))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[29\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.300:1.300:1.300) (1.189:1.189:1.189))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.300:1.300:1.300) (1.189:1.189:1.189)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.300:1.300:1.300) (1.189:1.189:1.189)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.300:1.300:1.300) (1.189:1.189:1.189)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.300:1.300:1.300) (1.189:1.189:1.189)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.383:0.383:0.383))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.383:0.383:0.383))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.014:0.014:0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.001:0.001:0.001))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.001:0.001:0.001))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[2\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.623:1.623:1.623) (1.392:1.392:1.392))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.623:1.623:1.623) (1.392:1.392:1.392)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.623:1.623:1.623) (1.392:1.392:1.392)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.623:1.623:1.623) (1.392:1.392:1.392)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.623:1.623:1.623) (1.392:1.392:1.392)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.399:0.400:0.401))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.399:0.400:0.401))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.003:0.002:0.001))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.013:0.011:0.010))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.470:0.470:0.470))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.470:0.470:0.470))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.448:-0.448:-0.448))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.448:-0.448:-0.448))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[30\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.214:1.214:1.214) (1.134:1.134:1.134))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.214:1.214:1.214) (1.134:1.134:1.134)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.214:1.214:1.214) (1.134:1.134:1.134)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.214:1.214:1.214) (1.134:1.134:1.134)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.214:1.214:1.214) (1.134:1.134:1.134)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.543:0.543:0.543))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.544:0.544:0.544))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.418:0.418:0.418))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.445:-0.445:-0.445))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.445:-0.445:-0.445))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.453:-0.453:-0.453))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.453:-0.453:-0.453))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[31\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.299:1.299:1.299) (1.188:1.188:1.188)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.383:0.383:0.383))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.383:0.383:0.383))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.014:0.014:0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.823:1.823:1.823))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.417:0.417:0.417))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.458:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[32\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.148:1.148:1.148) (1.092:1.092:1.092))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.148:1.148:1.148) (1.092:1.092:1.092)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.148:1.148:1.148) (1.092:1.092:1.092)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.148:1.148:1.148) (1.092:1.092:1.092)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.148:1.148:1.148) (1.092:1.092:1.092)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.016:0.016:0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.429:0.429:0.429))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.453:-0.453:-0.453))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.453:-0.453:-0.453))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[33\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.262:1.262:1.262) (1.165:1.165:1.165))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.262:1.262:1.262) (1.165:1.165:1.165)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.262:1.262:1.262) (1.165:1.165:1.165)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.262:1.262:1.262) (1.165:1.165:1.165)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.262:1.262:1.262) (1.165:1.165:1.165)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.382:0.382:0.382))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.408:0.408:0.408))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.462:-0.462:-0.461))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.001:0.001:0.001))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.462:-0.462:-0.461))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.001:0.001:0.001))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[34\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.793:0.793:0.793) (0.837:0.837:0.837))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.793:0.793:0.793) (0.836:0.836:0.836)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.793:0.793:0.793) (0.837:0.837:0.837)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.793:0.793:0.793) (0.836:0.836:0.836)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.793:0.793:0.793) (0.836:0.836:0.836)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.383:0.383:0.383))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.557:0.557))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.383:0.383:0.383))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.014:0.014:0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.424:0.424:0.424))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.455:-0.455:-0.455))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.005:-0.005:-0.005))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.455:-0.455:-0.455))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.005:-0.005:-0.005))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[35\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.799:0.799:0.799) (0.842:0.842:0.842))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.799:0.799:0.799) (0.841:0.841:0.841)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.799:0.799:0.799) (0.842:0.842:0.842)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.799:0.799:0.799) (0.841:0.841:0.841)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.799:0.799:0.799) (0.841:0.841:0.841)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.556:0.556:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.381:0.381:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.015:0.015:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.561:0.561:0.561))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[36\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.815:0.815:0.815) (0.855:0.855:0.855))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.815:0.815:0.815) (0.855:0.855:0.855)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.815:0.815:0.815) (0.855:0.855:0.855)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.815:0.815:0.815) (0.855:0.855:0.855)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.554:0.554))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:0.017:0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[37\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.069:1.069:1.069) (1.040:1.040:1.040))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.069:1.069:1.069) (1.040:1.040:1.040)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.069:1.069:1.069) (1.040:1.040:1.040)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.069:1.069:1.069) (1.040:1.040:1.040)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.069:1.069:1.069) (1.040:1.040:1.040)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.378:0.378))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.378:0.378))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:0.017:0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[38\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.800:0.800:0.800) (0.843:0.843:0.843))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.800:0.800:0.800) (0.842:0.842:0.842)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.800:0.800:0.800) (0.843:0.843:0.843)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.800:0.800:0.800) (0.842:0.842:0.842)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.800:0.800:0.800) (0.843:0.843:0.843)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.021:0.021:0.021))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.461:-0.461:-0.461))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.024:0.024:0.024))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.397:0.397:0.397))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.397:0.397:0.397))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.005:0.005:0.005))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.005:0.005:0.005))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[39\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.847:0.847:0.847) (0.884:0.884:0.884))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.848:0.848:0.848) (0.883:0.883:0.883)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.848:0.848:0.848) (0.884:0.884:0.884)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.847:0.847:0.847) (0.883:0.883:0.883)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.847:0.847:0.847) (0.884:0.884:0.884)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:0.017:0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[3\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.565:1.565:1.565) (1.356:1.356:1.356))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.565:1.565:1.565) (1.356:1.356:1.356)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.565:1.565:1.565) (1.356:1.356:1.356)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.565:1.565:1.565) (1.356:1.356:1.356)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.565:1.565:1.565) (1.356:1.356:1.356)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.552:0.550))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.389:0.401:0.413))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.552:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.389:0.401:0.413))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.456:-0.454))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.011:0.000:-0.011))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.456:-0.454))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.009:-0.001))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.548:0.548:0.548))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.548:0.548:0.548))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.478:0.478:0.478))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.448:-0.448:-0.448))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.029:-0.029:-0.029))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.448:-0.448:-0.448))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.029:-0.029:-0.029))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[40\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.812:0.812:0.812) (0.853:0.853:0.853))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.812:0.812:0.812) (0.853:0.853:0.853)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.812:0.812:0.812) (0.853:0.853:0.853)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.812:0.812:0.812) (0.853:0.853:0.853)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.812:0.812:0.812) (0.853:0.853:0.853)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.555:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.381:0.384))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.555:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.381:0.384))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.459:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.016:0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.459:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.378:0.378:0.378))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.378:0.378:0.378))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.017:0.017:0.017))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.017:0.017:0.017))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[41\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.398:0.419))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.398:0.419))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.001:-0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.455))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.006:-0.007))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[42\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.853:0.853:0.853) (0.888:0.888:0.888))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.854:0.854:0.854) (0.888:0.888:0.888)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.854:0.854:0.854) (0.888:0.888:0.888)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.853:0.853:0.853) (0.888:0.888:0.888)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.853:0.853:0.853) (0.888:0.888:0.888)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.399:0.421))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.399:0.421))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:-0.000:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.005:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[43\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.801:0.801:0.801) (0.844:0.844:0.844))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.801:0.801:0.801) (0.844:0.844:0.844)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.802:0.802:0.802) (0.844:0.844:0.844)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.801:0.801:0.801) (0.844:0.844:0.844)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.801:0.801:0.801) (0.844:0.844:0.844)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.550))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.403:0.427))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.403:0.427))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.456:-0.454))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:-0.001:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.456:-0.454))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.004:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.017:0.016:0.016))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.017:0.016:0.016))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[44\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.796:0.796:0.796) (0.839:0.839:0.839))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.796:0.796:0.796) (0.839:0.839:0.839)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.796:0.796:0.796) (0.839:0.839:0.839)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.796:0.796:0.796) (0.839:0.839:0.839)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.795:0.795:0.795) (0.839:0.839:0.839)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.555:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.381:0.384))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.555:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.381:0.384))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.459:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.016:0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.459:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[45\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.817:0.817:0.817) (0.857:0.857:0.857))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.817:0.817:0.817) (0.857:0.857:0.857)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.817:0.817:0.817) (0.857:0.857:0.857)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.817:0.817:0.817) (0.857:0.857:0.857)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.817:0.817:0.817) (0.857:0.857:0.857)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.398:0.419))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.398:0.419))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.001:-0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.455))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.005:-0.007))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[46\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.550:0.548))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.550:0.548))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.416))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.455:-0.452))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.002:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.455:-0.452))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.007:-0.005))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[47\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.550:0.546))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.400:0.420))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.551:0.547))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.400:0.420))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.451))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:-0.000:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.451))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.005:-0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[48\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.821:0.821:0.821) (0.861:0.861:0.861))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.821:0.821:0.821) (0.861:0.861:0.861)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.821:0.821:0.821) (0.861:0.861:0.861)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.821:0.821:0.821) (0.861:0.861:0.861)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.821:0.821:0.821) (0.861:0.861:0.861)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.551:0.553))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.379:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.551:0.553))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.379:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.457:-0.458:-0.458))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.017:0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.457:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[49\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.816:0.816:0.816) (0.856:0.856:0.856))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.816:0.816:0.816) (0.856:0.856:0.856)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.816:0.816:0.816) (0.856:0.856:0.856)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.816:0.816:0.816) (0.856:0.856:0.856)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.816:0.816:0.816) (0.856:0.856:0.856)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.550:0.547))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.433:0.489))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.550:0.547))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.433:0.489))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.451))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:-0.004:-0.025))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.451))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:-0.001:-0.020))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.018:0.018))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.018:0.018))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[4\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.669:1.669:1.669) (1.421:1.421:1.421))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.669:1.669:1.669) (1.421:1.421:1.421)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.669:1.669:1.669) (1.421:1.421:1.421)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.669:1.669:1.669) (1.421:1.421:1.421)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.669:1.669:1.669) (1.421:1.421:1.421)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.553:0.551))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.399:0.404:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.553:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.399:0.404:0.410))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.003:-0.002:-0.008))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.013:0.007:0.002))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.469:0.469:0.469))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.549:0.549:0.549))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.469:0.469:0.469))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.448:-0.448:-0.448))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.448:-0.448:-0.448))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.025:-0.025:-0.025))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[50\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.833:0.833:0.833) (0.871:0.871:0.871))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.833:0.833:0.833) (0.871:0.871:0.871)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.833:0.833:0.833) (0.871:0.871:0.871)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.833:0.833:0.833) (0.871:0.871:0.871)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.833:0.833:0.833) (0.871:0.871:0.871)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.418))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.001:-0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.456))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.006:-0.006))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[51\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.550:0.547))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.399:0.420))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.551:0.547))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.399:0.420))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.451))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:-0.000:-0.017))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.451))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.005:-0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[52\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.551:0.552))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.379:0.381))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.551:0.552))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.379:0.381))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.457:-0.458:-0.458))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.017:0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.457:-0.458:-0.458))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.838:-1.838:-1.838))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[53\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.800:0.800:0.800) (0.843:0.843:0.843))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.800:0.800:0.800) (0.842:0.842:0.842)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.800:0.800:0.800) (0.843:0.843:0.843)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.800:0.800:0.800) (0.842:0.842:0.842)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.800:0.800:0.800) (0.842:0.842:0.842)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.550:0.546))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.402:0.425))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.551:0.547))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.402:0.425))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.450))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:-0.001:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.450))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.004:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.880:1.880:1.880))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[54\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.808:0.808:0.808) (0.850:0.850:0.850))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.808:0.808:0.808) (0.850:0.850:0.850)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.808:0.808:0.808) (0.850:0.850:0.850)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.808:0.808:0.808) (0.850:0.850:0.850)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.808:0.808:0.808) (0.850:0.850:0.850)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.023:0.023:0.023))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[55\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.809:0.809:0.809) (0.850:0.850:0.850))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.809:0.809:0.809) (0.850:0.850:0.850)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.809:0.809:0.809) (0.850:0.850:0.850)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.809:0.809:0.809) (0.850:0.850:0.850)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.809:0.809:0.809) (0.850:0.850:0.850)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.551:0.546))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.401:0.423))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.551:0.547))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.379:0.401:0.423))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.450))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.016:-0.001:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.450))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.004:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[56\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.819:0.819:0.819) (0.860:0.860:0.860))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.820:0.820:0.820) (0.860:0.860:0.860)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.819:0.819:0.819) (0.859:0.859:0.859)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.819:0.819:0.819) (0.860:0.860:0.860)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.550:0.550:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.376:0.376:0.376))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.460:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.023:0.023:0.023))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[57\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.550:0.548))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.416))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.550:0.548))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.416))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.452))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.002:-0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.455:-0.452))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.007:-0.005))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.684:-0.684:-0.684))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[58\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.814:0.814:0.814) (0.854:0.854:0.854)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.814:0.814:0.814) (0.855:0.855:0.855)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.550))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.403:0.428))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.403:0.428))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.456:-0.454))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:-0.001:-0.019))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.456:-0.454))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.004:-0.010))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[59\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.840:0.840:0.840) (0.878:0.878:0.878))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.840:0.840:0.840) (0.878:0.878:0.878)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.840:0.840:0.840) (0.878:0.878:0.878)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.840:0.840:0.840) (0.877:0.877:0.877)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.840:0.840:0.840) (0.878:0.878:0.878)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.418))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.002:-0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.456))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.020:0.007:-0.006))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[5\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.870:0.870:0.870) (0.900:0.900:0.900))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.870:0.870:0.870) (0.900:0.900:0.900)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.870:0.870:0.870) (0.900:0.900:0.900)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.870:0.870:0.870) (0.900:0.900:0.900)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.870:0.870:0.870) (0.900:0.900:0.900)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.554:0.551))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.387:0.399:0.410))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.557:0.554:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.387:0.399:0.410))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.458:-0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.012:0.002:-0.008))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.460:-0.458:-0.455))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.010:0.001))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.546:0.546:0.546))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.546:0.546:0.546))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.485:0.485:0.485))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.445:-0.445:-0.445))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.032:-0.032:-0.032))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.445:-0.445:-0.445))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.032:-0.032:-0.032))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[60\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.808:0.808:0.808) (0.849:0.849:0.849))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.808:0.808:0.808) (0.849:0.849:0.849)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.808:0.808:0.808) (0.849:0.849:0.849)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.808:0.808:0.808) (0.849:0.849:0.849)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.807:0.807:0.807) (0.849:0.849:0.849)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.399:0.422))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.399:0.422))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.000:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.005:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.378:0.378:0.378))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.378:0.378:0.378))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.017:0.017:0.017))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.017:0.017:0.017))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[61\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.829:0.829:0.829) (0.868:0.868:0.868))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.829:0.829:0.829) (0.868:0.868:0.868)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.829:0.829:0.829) (0.868:0.868:0.868)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.829:0.829:0.829) (0.867:0.867:0.867)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.829:0.829:0.829) (0.868:0.868:0.868)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.418))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.418))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.002:-0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.456))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.020:0.007:-0.006))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.019:0.019:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[62\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.801:0.801:0.801) (0.843:0.843:0.843))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.801:0.801:0.801) (0.843:0.843:0.843)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.801:0.801:0.801) (0.843:0.843:0.843)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.801:0.801:0.801) (0.843:0.843:0.843)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.801:0.801:0.801) (0.843:0.843:0.843)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.417))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.417))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.002:-0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.458:-0.457:-0.456))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.020:0.007:-0.006))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[63\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.799:0.799:0.799) (0.842:0.842:0.842))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.800:0.800:0.800) (0.842:0.842:0.842)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.800:0.800:0.800) (0.842:0.842:0.842)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.799:0.799:0.799) (0.842:0.842:0.842)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.799:0.799:0.799) (0.842:0.842:0.842)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.552:0.549))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.405:0.432))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.552:0.549))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.405:0.432))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.456:-0.453))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:-0.001:-0.019))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.456:-0.453))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.004:-0.010))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.742:0.742:0.742))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[64\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.803:0.803:0.803) (0.846:0.846:0.846))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.803:0.803:0.803) (0.846:0.846:0.846)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.550))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.400:0.423))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.550))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.400:0.423))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:-0.000:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.005:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[65\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.855:0.855:0.855) (0.889:0.889:0.889))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.855:0.855:0.855) (0.889:0.889:0.889)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.855:0.855:0.855) (0.889:0.889:0.889)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.855:0.855:0.855) (0.889:0.889:0.889)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.855:0.855:0.855) (0.889:0.889:0.889)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.551))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.400:0.423))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.552:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.400:0.423))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:-0.000:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.005:-0.009))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.019))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.019))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[66\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.857:0.857:0.857) (0.891:0.891:0.891)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.417))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.552))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.397:0.417))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.019:0.002:-0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.456))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.020:0.007:-0.006))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.840:-1.840:-1.840))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.016:0.016:0.016))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.016:0.016:0.016))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[67\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.829:0.829:0.829) (0.868:0.868:0.868))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.829:0.829:0.829) (0.868:0.868:0.868)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.829:0.829:0.829) (0.868:0.868:0.868)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.829:0.829:0.829) (0.868:0.868:0.868)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.829:0.829:0.829) (0.868:0.868:0.868)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.399:0.420))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.552:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.399:0.420))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:-0.000:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.455))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.005:-0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.379:0.379:0.379))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.016:0.016:0.016))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.466:-0.466:-0.466))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.016:0.016:0.016))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[68\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.802:0.802:0.802) (0.844:0.844:0.844))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.802:0.802:0.802) (0.844:0.844:0.844)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.802:0.802:0.802) (0.844:0.844:0.844)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.802:0.802:0.802) (0.844:0.844:0.844)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.802:0.802:0.802) (0.844:0.844:0.844)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.555:0.556))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.381:0.384))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.553:0.555:0.556))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.377:0.381:0.384))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.460))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.016:0.014))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.460))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.559:0.559:0.559))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.467:-0.467:-0.467))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[69\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (0.803:0.803:0.803) (0.845:0.845:0.845)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.553:0.551))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.398:0.417))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.554:0.553:0.551))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.378:0.398:0.417))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.456))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.017:0.001:-0.015))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.457:-0.456))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.006:-0.006))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.560:0.560:0.560))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.377:0.377:0.377))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.468:-0.468:-0.468))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[6\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.438:1.438:1.438) (1.276:1.276:1.276))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.438:1.438:1.438) (1.276:1.276:1.276)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.438:1.438:1.438) (1.276:1.276:1.276)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.438:1.438:1.438) (1.276:1.276:1.276)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.438:1.438:1.438) (1.276:1.276:1.276)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.542:0.542:0.542))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.544:0.544:0.544))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.419:0.419:0.419))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.445:-0.445:-0.445))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.445:-0.445:-0.445))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.007:-0.007:-0.007))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.380:0.380:0.380))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.558:0.558:0.558))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.380:0.380:0.380))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.016:0.016:0.016))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.465:-0.465:-0.465))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.016:0.016:0.016))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[7\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.330:1.330:1.330) (1.208:1.208:1.208))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.330:1.330:1.330) (1.208:1.208:1.208)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.330:1.330:1.330) (1.208:1.208:1.208)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.330:1.330:1.330) (1.208:1.208:1.208)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.330:1.330:1.330) (1.208:1.208:1.208)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.542:0.542:0.542))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.544:0.544:0.544))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.420:0.420:0.420))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.445:-0.445:-0.445))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.018:-0.018:-0.018))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.445:-0.445:-0.445))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.008:-0.008:-0.008))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.551:0.551:0.551))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.450:0.450:0.450))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.450:-0.450:-0.450))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.450:-0.450:-0.450))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.016:-0.016:-0.016))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[8\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.378:1.378:1.378) (1.238:1.238:1.238))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.378:1.378:1.378) (1.238:1.238:1.238)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.378:1.378:1.378) (1.238:1.238:1.238)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.378:1.378:1.378) (1.238:1.238:1.238)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.378:1.378:1.378) (1.238:1.238:1.238)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.546:0.546:0.546))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.405:0.405:0.405))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.547:0.547:0.547))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.405:0.405:0.405))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.450:-0.450:-0.450))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.003:-0.003:-0.003))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.450:-0.450:-0.450))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.007:0.007:0.007))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.433:0.433:0.434))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.553:0.553:0.553))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.433:0.433:0.434))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.009:-0.009:-0.009))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
(CELL
(CELLTYPE "gf180mcu_fd_sc_mcu7t5v0__sdffq_1")
(INSTANCE u_scanchain_local\.scan_flop\[9\])
(DELAY
(ABSOLUTE
(IOPATH CLK Q (1.371:1.371:1.371) (1.234:1.234:1.234))
(COND D===1'b1 && SE===1'b1
(IOPATH CLK Q (1.371:1.371:1.371) (1.234:1.234:1.234)))
(COND D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0
(IOPATH CLK Q (1.371:1.371:1.371) (1.234:1.234:1.234)))
(COND SE===1'b0 && SI===1'b0
(IOPATH CLK Q (1.371:1.371:1.371) (1.234:1.234:1.234)))
(COND D===1'b0 && SI===1'b1
(IOPATH CLK Q (1.371:1.371:1.371) (1.234:1.234:1.234)))
)
)
(TIMINGCHECK
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.386:0.386:0.386))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.555:0.555:0.555))
(SETUP (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.386:0.386:0.386))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_D_AND_SE === 1'b1 (posedge CLK)) (0.013:0.013:0.013))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (-0.459:-0.459:-0.459))
(HOLD (COND ENABLE_NOT_D_AND_SE === 1'b1 (negedge SI)) (COND ENABLE_NOT_D_AND_SE === 1'b1 (posedge CLK)) (0.018:0.018:0.018))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.154:-0.154:-0.154))
(SETUP (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (1.881:1.881:1.881))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.153:0.153:0.153))
(SETUP (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (1.822:1.822:1.822))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (0.743:0.743:0.743))
(HOLD (COND ENABLE_D_AND_NOT_SI === 1'b1 (negedge SE)) (COND ENABLE_D_AND_NOT_SI === 1'b1 (posedge CLK)) (-1.839:-1.839:-1.839))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (0.020:0.020:0.020))
(HOLD (COND ENABLE_NOT_D_AND_SI === 1'b1 (negedge SE)) (COND ENABLE_NOT_D_AND_SI === 1'b1 (posedge CLK)) (-0.685:-0.685:-0.685))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (0.441:0.441:0.441))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.552:0.552:0.552))
(SETUP (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (0.441:0.441:0.441))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.451:-0.451:-0.451))
(HOLD (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (negedge D)) (COND ENABLE_NOT_SE_AND_NOT_SI === 1'b1 (posedge CLK)) (-0.012:-0.012:-0.012))
(WIDTH (posedge CLK) (0.358:0.358:0.358))
(WIDTH (negedge CLK) (0.669:0.669:0.669))
(PERIOD CLK (1.338:1.338:1.338))
)
)
)