commit | dc24d54a166d86ae4896e1a7b0fdb6d12f3c3582 | [log] [tgz] |
---|---|---|
author | tinybot <bot@tinytapeout.com> | Sun Dec 04 21:06:40 2022 +0000 |
committer | tinybot <bot@tinytapeout.com> | Sun Dec 04 21:06:40 2022 +0000 |
tree | 9c3affed0b8890e658e3462207667b6c177af2ee | |
parent | ae4d7ef032a0181c078bcf7584e390ee6b9480d2 [diff] |
harden project [skip ci]
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.