| commit | ae4d7ef032a0181c078bcf7584e390ee6b9480d2 | [log] [tgz] |
|---|---|---|
| author | Greg Davill <greg.davill@gmail.com> | Mon Dec 05 07:18:10 2022 +1030 |
| committer | Greg Davill <greg.davill@gmail.com> | Mon Dec 05 07:18:10 2022 +1030 |
| tree | 4594833003da6efc52da3a191d9be7d9e1c21b58 | |
| parent | 07b4d7e86ede2bbe21e9c81c18e221e99684985d [diff] |
rtl: fix invalid gpio config
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.