commit | adc25d0fbbbac2021b4e5ebc2d244b83c8451965 | [log] [tgz] |
---|---|---|
author | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 12 21:34:53 2022 -0800 |
committer | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 12 21:34:53 2022 -0800 |
tree | 09707663c4b3beb53fba7ce68ee263e200e63eaa | |
parent | 6b35f4a50e556ebfc074fd678b3a460644b529bf [diff] |
final gds oasis
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.