commit | 6b35f4a50e556ebfc074fd678b3a460644b529bf | [log] [tgz] |
---|---|---|
author | tinybot <bot@tinytapeout.com> | Mon Dec 05 14:46:10 2022 +0000 |
committer | tinybot <bot@tinytapeout.com> | Mon Dec 05 14:46:10 2022 +0000 |
tree | bdc509190f5fd1364dad274a7a5799b5d0397e52 | |
parent | dde4a146ec4b0cf129b247202d7eab979fb0f6e4 [diff] |
harden project [skip ci]
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.