commit | dde4a146ec4b0cf129b247202d7eab979fb0f6e4 | [log] [tgz] |
---|---|---|
author | Greg Davill <greg.davill@gmail.com> | Tue Dec 06 00:53:13 2022 +1030 |
committer | Greg Davill <greg.davill@gmail.com> | Tue Dec 06 00:53:13 2022 +1030 |
tree | dae07a889221fa4e4b85d87fce47ca5b5701c4fe | |
parent | 04b51ee3d3e8f1258dc60caf4ece37037c4e2965 [diff] |
rtl: Adjust rf_ram_if for single port memory Bump up macro serv_0 size to assist with routing
An award winning CPU design fit into the GF180 MPW0 Shuttle.
To keep the design simple this project places a Serv CPU with a scan-chain around it connecting it's wishbone bus which is a combination of data and instructions out via I/O pins.
Another I/O pin is responsible for handling clock and reset. Operation will run as follows:
In this manner we should be able to implement external peripherals like UARTs, timers, and GPIOs. The external controller can be a microcontroller, FPGA, or the caravel harness SoC.