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foss-eda-tools / third_party / opencircuitdesign.com / open_pdks / c664d8ced0de2f48a5d6dd733d78aec244341883 / . / sky130 / magic / sky130.tech
blob: cf0940551255d475f00a4a6ccaad16faf6612fca [file] [log] [blame]
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1###
2### Source file sky130.tech
3### Process this file with the preproc.py macro processor
4### Note that the tech name is always TECHNAME for
5### magic; this keeps compatibility between layouts
6### for all process variants.
7###
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]8#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]9# Copyright (c) 2020 R. Timothy Edwards
10# Revisions: See below
11#
12# This file is an Open Source foundry process describing
Tim Edwardsb4da28f2020-07-25 16:43:32 -0400[diff] [blame]13# the SkyWater sky130 hybrid 0.18um / 0.13um fabrication
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]14# process. The file may be distributed under the terms
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]15# of the Apache 2.0 license agreement.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]16#
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]17#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]18# This file is designed to be used with magic versions
19# 8.3.24 or newer.
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]20#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]21tech
22 format 35
23 TECHNAME
24end
25
26version
27 version REVISION
28 description "SkyWater SKY130: PRE ALPHA Vendor Open Source rules and DRC"
29end
30
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]31#------------------------------------------------------------------------
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]32# Status 7/10/20: Rev 1 (alpha):
Tim Edwardsab5bae82020-07-05 17:40:59 -0400[diff] [blame]33# First public release
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]34# Status 8/14/20: Rev 2 (alpha):
35# Started updating with new device/model naming convention
36#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]37
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]38#------------------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]39# Supported device types
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]40#------------------------------------------------------------------------
41# device name magic ID layer description
42#------------------------------------------------------------------------
43# sky130_fd_pr__nfet_01v8 nfet standard nFET
44# sky130_fd_pr__nfet_01v8 scnfet standard nFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]45# sky130_fd_pr__special_nfet_latch npd special nFET in SRAM cell
46# sky130_fd_pr__special_nfet_pass npass special nFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]47# sky130_fd_pr__nfet_01v8_lvt nfetlvt low Vt nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]48# sky130_fd_bs_flash__special_sonosfet_star nsonos SONOS nFET
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]49# sky130_fd_pr__pfet_01v8 pfet standard pFET
50# sky130_fd_pr__pfet_01v8 scpfet standard pFET in standard cell**
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]51# sky130_fd_pr__special_pfet_pass ppu special pFET in SRAM cell
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]52# sky130_fd_pr__pfet_01v8_lvt pfetlvt low Vt pFET
53# sky130_fd_pr__pfet_01v8_mvt pfetmvt med Vt pFET
54# sky130_fd_pr__pfet_01v8_hvt pfethvt high Vt pFET
55# sky130_fd_pr__nfet_03v3_nvt --- native nFET
56# sky130_fd_pr__pfet_g5v0d10v5 mvpfet thickox pFET
57# sky130_fd_pr__nfet_g5v0d10v5 mvnfet thickox nFET
58# sky130_fd_pr__nfet_01v8_nvt mvnnfet thickox native nFET
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]59# sky130_fd_pr__diode_pw2nd_05v5 ndiode n+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]60# sky130_fd_pr__diode_pw2nd_05v5_lvt ndiodelvt low Vt n+ diff diode
61# sky130_fd_pr__diode_pw2nd_05v5_nvt nndiode diode with nndiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]62# sky130_fd_pr__diode_pw2nd_11v0 mvndiode thickox n+ diff diode
63# sky130_fd_pr__diode_pd2nw_05v5 pdiode p+ diff diode
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]64# sky130_fd_pr__diode_pd2nw_05v5_lvt pdiodelvt low Vt p+ diff diode
65# sky130_fd_pr__diode_pd2nw_05v5_hvt pdiodehvt high Vt p+ diff diode
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]66# sky130_fd_pr__diode_pd2nw_11v0 mvpdiode thickox p+ diff diode
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]67# sky130_fd_pr__npn_05v0 pbase NPN in deep nwell
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]68# sky130_fd_pr__npn_11v0 pbase thick oxide gated NPN
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]69# sky130_fd_pr__pnp_05v0 nbase PNP
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]70# sky130_fd_pr__cap_mim_m3_1 mimcap MiM cap 1st plate
71# sky130_fd_pr__cap_mim_m3_2 mimcap2 MiM cap 2nd plate
72# sky130_fd_pr__res_generic_nd rdn n+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]73# sky130_fd_pr__res_generic_nd__hv mvrdn thickox n+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]74# sky130_fd_pr__res_generic_pd rdp p+ diff resistor
Tim Edwards69901142020-09-21 15:09:56 -0400[diff] [blame]75# sky130_fd_pr__res_generic_pd__nv mvrdp thickox p+ diff resistor
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]76# sky130_fd_pr__res_generic_l1 rli local interconnect resistor
77# sky130_fd_pr__res_generic_po npres n+ poly resistor
78# sky130_fd_pr__res_high_po_* ppres (*) p+ poly resistor (300 Ohms/sq)
79# sky130_fd_pr__res_xhigh_po_* xres (*) p+ poly resistor (2k Ohms/sq)
80# sky130_fd_pr__cap_var_lvt varactor low Vt varactor
81# sky130_fd_pr__cap_var_hvt varactorhvt high Vt varactor
82# sky130_fd_pr__cap_var mvvaractor thickox varactor
83# sky130_fd_pr__res_iso_pw rpw pwell resistor (in deep nwell)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]84#
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]85# (*) Note that ppres may extract into some generic type called
86# "sky130_fd_pr__res_xhigh_po", but only specific sizes of xhrpoly are
87# allowed, and these are created from fixed layouts like the types below.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]88#
89# (**) nFET and pFET in standard cells are the same as devices
90# outside of the standard cell except for the DRC rule for
91# FET to diffusion contact spacing (which is 0.05um, not 0.055um)
92#
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]93#-------------------------------------------------------------
94# The following devices are not extracted but are represented
95# only by script-generated subcells in the PDK.
96#-------------------------------------------------------------
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]97# sky130_fd_pr__esd_nfet_01v8 ESD nFET
98# sky130_fd_pr__esd_nfet_g5v0d10v5 ESD thickox nFET
99# sky130_fd_pr__esd_nfet_05v0_nvt ESD native nFET
100# sky130_fd_pr__esd_pfet_g5v0d10v5 ESD thickox pFET
101# sky130_fd_pr__special_nfet_pass_flash flash nFET device
102# sky130_fd_pr__esd_rf_diode_pw2nd_11v0 ESD n+ diode
103# sky130_fd_pr__esd_rf_diode_pd2nw_11v0 ESD p+ diode
104# sky130_fd_pr__cap_vpp_* Vpp cap
105# sky130_fd_pr__ind_* inductor
106# sky130_fd_pr__fuse_m4 metal fuse device
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]107#--------------------------------------------------------------
108
109#-----------------------------------------------------
110# Tile planes
111#-----------------------------------------------------
112
113planes
114 dwell,dw
115 well,w
116 active,a
117 locali,li1,li
118 metal1,m1
119 metal2,m2
120 metal3,m3
121#ifdef METAL5
122#ifdef MIM
123 cap1,c1
124#endif (MIM)
125 metal4,m4
126#ifdef MIM
127 cap2,c2
128#endif (MIM)
129 metal5,m5
130#endif (METAL5)
131#ifdef REDISTRIBUTION
132 metali,mi
133#endif
134 block,b
135 comment,c
136end
137
138#-----------------------------------------------------
139# Tile types
140#-----------------------------------------------------
141
142types
143# Deep nwell
144 dwell dnwell,dnw
145
146# Wells
147 well nwell,nw
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]148 well pwell,pw
149 well rpw,rpwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]150 -well obswell
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]151 well pbase,npn
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]152 well nbase,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]153
154# Transistors
155 active nmos,ntransistor,nfet
156 -active scnmos,scntransistor,scnfet
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]157 -active npd,npdfet,sramnfet
158 -active npass,npassfet,srampassfet
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]159 active pmos,ptransistor,pfet
160 -active scpmos,scptransistor,scpfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]161 -active scpmoshvt,scpfethvt
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]162 -active ppu,ppufet,srampfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]163 active nnmos,nntransistor
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]164 active mvnmos,mvntransistor,mvnfet
165 active mvpmos,mvptransistor,mvpfet
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]166 active mvnnmos,mvnntransistor,mvnnfet,nnfet
167 active varactor,varact,var
168 active mvvaractor,mvvaract,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]169
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]170 active pmoslvt,pfetlvt
171 active pmosmvt,pfetmvt
172 active pmoshvt,pfethvt
173 active nmoslvt,nfetlvt
174 active varactorhvt,varacthvt,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]175 -active nsonos,sonos
176
177# Diffusions
178 active ndiff,ndiffusion,ndif
179 active pdiff,pdiffusion,pdif
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]180 active mvndiff,mvndiffusion,mvndif
181 active mvpdiff,mvpdiffusion,mvpdif
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]182 active ndiffc,ndcontact,ndc
183 active pdiffc,pdcontact,pdc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]184 active mvndiffc,mvndcontact,mvndc
185 active mvpdiffc,mvpdcontact,mvpdc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]186 active psubdiff,psubstratepdiff,ppdiff,ppd,psd
187 active nsubdiff,nsubstratendiff,nndiff,nnd,nsd
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]188 active mvpsubdiff,mvpsubstratepdiff,mvppdiff,mvppd,mvpsd
189 active mvnsubdiff,mvnsubstratendiff,mvnndiff,mvnnd,mvnsd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]190 active psubdiffcont,psubstratepcontact,psc
191 active nsubdiffcont,nsubstratencontact,nsc
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]192 active mvpsubdiffcont,mvpsubstratepcontact,mvpsc
193 active mvnsubdiffcont,mvnsubstratencontact,mvnsc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]194 -active obsactive
195 -active mvobsactive
196
197# Poly
198 active poly,p,polysilicon
199 active polycont,pc,pcontact,polycut,polyc
200 active xpolycontact,xpolyc,xpc
201
202# Resistors
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]203 active npolyres,npres,mrp1
204 active ppolyres,ppres,xhrpoly
205 active xpolyres,xpres,xres,uhrpoly
206 active ndiffres,rnd,rdn,rndiff
207 active pdiffres,rpd,rdp,rpdiff
208 active mvndiffres,mvrnd,mvrdn,mvrndiff
209 active mvpdiffres,mvrpd,mvrdp,mvrpdiff
210 active rmp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]211
212# Diodes
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]213 active pdiode,pdi
214 active ndiode,ndi
215 active nndiode,nndi
216 active pdiodec,pdic
217 active ndiodec,ndic
218 active nndiodec,nndic
219 active mvpdiode,mvpdi
220 active mvndiode,mvndi
221 active mvpdiodec,mvpdic
222 active mvndiodec,mvndic
223 active pdiodelvt,pdilvt
224 active pdiodehvt,pdihvt
225 active ndiodelvt,ndilvt
226 active pdiodelvtc,pdilvtc
227 active pdiodehvtc,pdihvtc
228 active ndiodelvtc,ndilvtc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]229
230# Local Interconnect
231 locali locali,li1,li
232 -locali corelocali,coreli1,coreli
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]233 locali rlocali,rli1,rli
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]234 locali viali,vial,mcon,lic,licon,m1c,v0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]235 -locali obsli1,obsli
236 -locali obsli1c,obslic,obslicon
237
238# Metal 1
239 metal1 metal1,m1,met1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]240 metal1 rmetal1,rm1,rmet1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]241 metal1 via1,m2contact,m2cut,m2c,via,v,v1
242 -metal1 obsm1
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]243 metal1 padl
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]244 -metal1 m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]245
246# Metal 2
247 metal2 metal2,m2,met2
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]248 metal2 rmetal2,rm2,rmet2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]249 metal2 via2,m3contact,m3cut,m3c,v2
250 -metal2 obsm2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]251 -metal2 m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]252
253# Metal 3
254 metal3 metal3,m3,met3
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]255 metal3 rmetal3,rm3,rmet3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]256 -metal3 obsm3
257#ifdef METAL5
258 metal3 via3,v3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]259 -metal3 m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]260
261#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]262 cap1 mimcap,mim,capm
263 cap1 mimcapcontact,mimcapc,mimcc,capmc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]264#endif
265
266# Metal 4
267 metal4 metal4,m4,met4
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]268 metal4 rmetal4,rm4,rmet4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]269 -metal4 obsm4
270 metal4 via4,v4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]271 -metal4 m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]272
273#ifdef MIM
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]274 cap2 mimcap2,mim2,capm2
275 cap2 mimcap2contact,mimcap2c,mim2cc,capm2c
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]276#endif
277
278# Metal 5
279 metal5 metal5,m5,met5
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]280 metal5 rm5,rmetal5,rmet5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]281 -metal5 obsm5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]282 -metal5 m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]283#endif (METAL5)
284
285#ifdef REDISTRIBUTION
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]286 metal5 mrdlcontact,mrdlc
287 metali metalrdl,mrdl,metrdl
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]288 -metali obsmrdl
289#endif (REDISTRIBUTION)
290
291# Miscellaneous
292 -block glass
293 -block fillblock
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]294 comment comment
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]295 -comment obscomment
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]296# fixed resistor width identifiers
297 -comment res0p35
298 -comment res0p69
299 -comment res1p41
300 -comment res2p85
301 -comment res5p73
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]302
303end
304
305#-----------------------------------------------------
306# Magic contact types
307#-----------------------------------------------------
308
309contact
310 pc poly locali
311 ndc ndiff locali
312 pdc pdiff locali
313 nsc nsd locali
314 psc psd locali
315 ndic ndiode locali
316 ndilvtc ndiodelvt locali
317 nndic nndiode locali
318 pdic pdiode locali
319 pdilvtc pdiodelvt locali
320 pdihvtc pdiodehvt locali
321 xpc xpc locali
322
323 mvndc mvndiff locali
324 mvpdc mvpdiff locali
325 mvnsc mvnsd locali
326 mvpsc mvpsd locali
327 mvndic mvndiode locali
328 mvpdic mvpdiode locali
329
330 lic locali metal1
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]331 obslic obsli metal1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]332
333 via1 metal1 metal2
334 via2 metal2 metal3
335#ifdef METAL5
336 via3 metal3 metal4
337 via4 metal4 metal5
338#endif (METAL5)
339 stackable
340
341#ifdef METAL5
342#ifdef MIM
343 # MiM cap contacts are not stackable!
344 mimcc mimcap metal4
345 mim2cc mimcap2 metal5
346#endif (MIM)
347
348 padl m1 m2 m3 m4 m5 glass
349#else
350 padl m1 m2 m3 glass
351#endif (!METAL5)
352
353#ifdef REDISTRIBUTION
354 mrdlc metal5 mrdl
355#endif (REDISTRIBUTION)
356end
357
358#-----------------------------------------------------
359# Layer aliases
360#-----------------------------------------------------
361
362aliases
363
364 allwellplane nwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]365 allnwell nwell,obswell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]366
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]367 allnfets nfet,npass,npd,scnfet,mvnfet,mvnnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]368 allpfets pfet,ppu,scpfet,scpfethvt,mvpfet,pfethvt,pfetlvt,pfetmvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]369 allfets allnfets,allpfets,varactor,mvvaractor,varhvt
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]370 allfetsstd nfet,mvnfet,mvnnfet,nfetlvt,pfet,mvpfet,pfethvt,pfetlvt,pfetmvt
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]371 allfetsspecial npass,npd,scnfet,nsonos,ppu,scpfet,scpfethvt
372 allfetsnolvt nfet,npass,npd,scnfet,mvnfet,mvnnfet,nsonos,pfet,ppu,scpfet,scpfethvt,mvpfet,pfethvt,pfetmvt,varactor,mvvaractor,varhvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]373
374 allnactivenonfet *ndiff,*nsd,*ndiode,*nndiode,*mvndiff,*mvnsd,*mvndiode,*ndiodelvt
375 allnactive allnactivenonfet,allnfets
376 allnactivenontap *ndiff,*ndiode,*nndiode,*mvndiff,*mvndiode,*ndiodelvt,allnfets
377 allnactivetap *nsd,*mvnsd,var,varhvt,mvvar
378
379 allpactivenonfet *pdiff,*psd,*pdiode,*mvpdiff,*mvpsd,*mvpdiode,*pdiodelvt,*pdiodehvt
380 allpactive allpactivenonfet,allpfets
381 allpactivenontap *pdiff,*pdiode,*mvpdiff,*mvpdiode,*pdiodelvt,*pdiodehvt,allpfets
382 allpactivetap *psd,*mvpsd
383
384 allactivenonfet allnactivenonfet,allpactivenonfet
385 allactive allactivenonfet,allfets
386
387 allactiveres ndiffres,pdiffres,mvndiffres,mvpdiffres
388
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]389 allndifflv *ndif,*nsd,*ndiode,ndiffres,nfet,npass,npd,scnfet,nfetlvt,nsonos
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]390 allpdifflv *pdif,*psd,*pdiode,pdiffres,pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt,pfethvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]391 alldifflv allndifflv,allpdifflv
392 allndifflvnonfet *ndif,*nsd,*ndiode,*nndiode,ndiffres,*ndiodelvt
393 allpdifflvnonfet *pdif,*psd,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt
394 alldifflvnonfet allndifflvnonfet,allpdifflvnonfet
395
396 allndiffmv *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
397 allpdiffmv *mvpdif,*mvpsd,*mvpdiode,mvpdiffres,mvpfet
398 alldiffmv allndiffmv,allpdiffmv
399 allndiffmvnontap *mvndif,*mvndiode,*nndiode,mvndiffres,mvnfet,mvnnfet
400 allpdiffmvnontap *mvpdif,*mvpdiode,mvpdiffres,mvpfet
401 alldiffmvnontap allndiffmvnontap,allpdiffmvnontap
402 allndiffmvnonfet *mvndif,*mvnsd,*mvndiode,*nndiode,mvndiffres
403 allpdiffmvnonfet *mvpdif,*mvpsd,*mvpdiode,mvpdiffres
404 alldiffmvnonfet allndiffmvnonfet,allpdiffmvnonfet
405
406 alldiffnonfet alldifflvnonfet,alldiffmvnonfet
407 alldiff alldifflv,alldiffmv
408
409 allpolyres mrp1,xhrpoly,uhrpoly,rmp
410 allpolynonfet *poly,allpolyres,xpc
411 allpolynonres *poly,allfets,xpc
412
413 allpoly allpolynonfet,allfets
414 allpolynoncap *poly,xpc,allfets,allpolyres
415
416 allndiffcontlv ndc,nsc,ndic,nndic,ndilvtc
417 allpdiffcontlv pdc,psc,pdic,pdilvtc,pdihvtc
418 allndiffcontmv mvndc,mvnsc,mvndic
419 allpdiffcontmv mvpdc,mvpsc,mvpdic
420 allndiffcont allndiffcontlv,allndiffcontmv
421 allpdiffcont allpdiffcontlv,allpdiffcontmv
422 alldiffcontlv allndiffcontlv,allpdiffcontlv
423 alldiffcontmv allndiffcontmv,allpdiffcontmv
424 alldiffcont alldiffcontlv,alldiffcontmv
425
426 allcont alldiffcont,pc
427
428 allres allpolyres,allactiveres
429
430 allli *locali,coreli,rli
431 allm1 *m1,rm1
432 allm2 *m2,rm2
433 allm3 *m3,rm3
434#ifdef METAL5
435 allm4 *m4,rm4
436 allm5 *m5,rm5
437#endif (METAL5)
438
439 allpad padl
440
441 psub pwell
442
443end
444
445#-----------------------------------------------------
446# Layer drawing styles
447#-----------------------------------------------------
448
449styles
450 styletype mos
451 dnwell cwell
452 nwell nwell
453 pwell pwell
454 rpwell pwell ptransistor_stripes
455 ndiff ndiffusion
456 pdiff pdiffusion
457 nsd ndiff_in_nwell
458 psd pdiff_in_pwell
459 nfet ntransistor ntransistor_stripes
460 scnfet ntransistor ntransistor_stripes
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]461 npass ntransistor ntransistor_stripes
462 npd ntransistor ntransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]463 pfet ptransistor ptransistor_stripes
464 scpfet ptransistor ptransistor_stripes
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]465 scpfethvt ptransistor ptransistor_stripes implant2
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]466 ppu ptransistor ptransistor_stripes
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]467 var polysilicon ndiff_in_nwell
468 ndc ndiffusion metal1 contact_X'es
469 pdc pdiffusion metal1 contact_X'es
470 nsc ndiff_in_nwell metal1 contact_X'es
471 psc pdiff_in_pwell metal1 contact_X'es
472
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]473 pnp nwell ntransistor_stripes
474 npn pwell ptransistor_stripes
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]475
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]476 pfetlvt ptransistor ptransistor_stripes implant1
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]477 pfetmvt ptransistor ptransistor_stripes implant3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]478 pfethvt ptransistor ptransistor_stripes implant2
479 nfetlvt ntransistor ntransistor_stripes implant1
480 nsonos ntransistor implant3
481 varhvt polysilicon ndiff_in_nwell implant2
482
483 mvndiff ndiffusion hvndiff_mask
484 mvpdiff pdiffusion hvpdiff_mask
485 mvnsd ndiff_in_nwell hvndiff_mask
486 mvpsd pdiff_in_pwell hvpdiff_mask
487 mvnfet ntransistor ntransistor_stripes hvndiff_mask
488 mvnnfet ntransistor ndiff_in_nwell hvndiff_mask
489 mvpfet ptransistor ptransistor_stripes
490 mvvar polysilicon ndiff_in_nwell hvndiff_mask
491 mvndc ndiffusion metal1 contact_X'es hvndiff_mask
492 mvpdc pdiffusion metal1 contact_X'es hvpdiff_mask
493 mvnsc ndiff_in_nwell metal1 contact_X'es hvndiff_mask
494 mvpsc pdiff_in_pwell metal1 contact_X'es hvpdiff_mask
495
496 poly polysilicon
497 pc polysilicon metal1 contact_X'es
498 npolyres polysilicon silicide_block nselect2
499 ppolyres polysilicon silicide_block pselect2
500 xpc polysilicon pselect2 metal1 contact_X'es
501 rmp polysilicon poly_resist_stripes
502
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]503 res0p35 implant1
504 res0p69 implant1
505 res1p41 implant1
506 res2p85 implant1
507 res5p73 implant1
508
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]509 pdiode pdiffusion pselect2
510 ndiode ndiffusion nselect2
511 pdiodec pdiffusion pselect2 metal1 contact_X'es
512 ndiodec ndiffusion nselect2 metal1 contact_X'es
513
514 nndiode ndiffusion nselect2 implant3
515 ndiodelvt ndiffusion nselect2 implant1
516 pdiodelvt pdiffusion pselect2 implant1
517 pdiodehvt pdiffusion pselect2 implant2
518 pdilvtc pdiffusion pselect2 implant1 metal1 contact_X'es
519 pdihvtc pdiffusion pselect2 implant2 metal1 contact_X'es
520 ndilvtc ndiffusion nselect2 implant1 metal1 contact_X'es
521
522 mvpdiode pdiffusion pselect2 hvpdiff_mask
523 mvndiode ndiffusion nselect2 hvndiff_mask
524 mvpdiodec pdiffusion pselect2 metal1 contact_X'es hvpdiff_mask
525 mvndiodec ndiffusion nselect2 metal1 contact_X'es hvndiff_mask
526 nndiodec ndiff_in_nwell nselect2 metal1 contact_X'es hvndiff_mask
527
528 locali metal1
529 coreli metal1
530 rli metal1 poly_resist_stripes
531 lic metal1 metal2 via1arrow
532 obsli metal1
533 obslic metal1 metal2 via1arrow
534
535 metal1 metal2
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]536 m1fill metal2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]537 rm1 metal2 poly_resist_stripes
538 obsm1 metal2
539 m2c metal2 metal3 via2arrow
540 metal2 metal3
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]541 m2fill metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]542 rm2 metal3 poly_resist_stripes
543 obsm2 metal3
544 m3c metal3 metal4 via3alt
545 metal3 metal4
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]546 m3fill metal4
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]547 rm3 metal4 poly_resist_stripes
548 obsm3 metal4
549#ifdef METAL5
550#ifdef MIM
551 mimcap metal3 mems
552 mimcc metal3 contact_X'es mems
553 mimcap2 metal4 mems
554 mim2cc metal4 contact_X'es mems
555#endif (MIM)
556 via3 metal4 metal5 via4
557 metal4 metal5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]558 m4fill metal5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]559 rm4 metal5 poly_resist_stripes
560 obsm4 metal5
561 via4 metal5 metal6 via5
562 metal5 metal6
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]563 m5fill metal6
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]564 rm5 metal6 poly_resist_stripes
565 obsm5 metal6
566#endif (METAL5)
567#ifdef REDISTRIBUTION
568 mrdlc metal6 metal7 via6
569 metalrdl metal7
570 obsmrdl metal7
571#endif (REDISTRIBUTION)
572
573 glass overglass
574 mrp1 poly_resist poly_resist_stripes
575 xhrpoly poly_resist silicide_block
576 uhrpoly poly_resist
577 ndiffres ndiffusion ndop_stripes
578 pdiffres pdiffusion pdop_stripes
579 mvndiffres ndiffusion hvndiff_mask ndop_stripes
580 mvpdiffres pdiffusion hvpdiff_mask pdop_stripes
581 comment comment
582 error_p error_waffle
583 error_s error_waffle
584 error_ps error_waffle
585 fillblock cwell
586
587 obswell cwell
588 obsactive implant4
589
590#ifndef METAL5
591 padl metal4 via4 overglass
592#else
593 padl metal6 via6 overglass
594#endif
595
596 magnet substrate_field_implant
597 rotate via3alt
598 fence via5
599end
600
601#-----------------------------------------------------
602# Special paint/erase rules
603#-----------------------------------------------------
604
605compose
606 compose nfet poly ndiff
607 compose pfet poly pdiff
608 compose var poly nsd
609
610 compose mvnfet poly mvndiff
611 compose mvpfet poly mvpdiff
612 compose mvvar poly mvnsd
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]613
614 paint obslic locali via1
Tim Edwardsd44d18d2020-09-22 15:29:11 -0400[diff] [blame]615 paint obslic obsm1 obsli,obsm1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]616
617 paint ndc nwell pdc
618 paint nfet nwell pfet
619 paint scnfet nwell scpfet
620 paint ndiff nwell pdiff
621 paint psd nwell nsd
622 paint psc nwell nsc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]623 paint npd nwell ppu
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]624
625 paint pdc pwell ndc
626 paint pfet pwell nfet
627 paint scpfet pwell scnfet
628 paint pdiff pwell ndiff
629 paint nsd pwell psd
630 paint nsc pwell psc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]631 paint ppu pwell npd
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]632
633 paint pdc coreli pdc
634 paint ndc coreli ndc
635 paint pc coreli pc
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]636 paint nsc coreli nsc
637 paint psc coreli psc
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]638 paint viali coreli viali
639
640 paint coreli pdc pdc
641 paint coreli ndc ndc
642 paint coreli pc pc
643 paint coreli nsc nsc
644 paint coreli psc psc
645 paint coreli viali viali
646
647#ifdef METAL5
648 paint m4 obsm4 m4
649 paint m5 obsm5 m5
650#endif (METAL5)
651end
652
653#-----------------------------------------------------
654# Electrical connectivity
655#-----------------------------------------------------
656
657connect
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]658 *nwell,*nsd,*mvnsd,dnwell,pnp *nwell,*nsd,*mvnsd,dnwell,pnp
659 pwell,*psd,*mvpsd,npn pwell,*psd,*mvpsd,npn
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]660 *li,coreli *li,coreli
Tim Edwards48db3e12020-09-22 15:41:41 -0400[diff] [blame]661 *m1,m1fill,obslic *m1,m1fill,obslic
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]662 *m2,m2fill *m2,m2fill
663 *m3,m3fill *m3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]664#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]665 *m4,m4fill *m4,m4fill
666 *m5,m5fill *m5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]667#ifdef MIM
668 *mimcap *mimcap
669 *mimcap2 *mimcap2
670#endif (MIM)
671#endif (METAL5)
672 allnactivenonfet allnactivenonfet
673 allpactivenonfet allpactivenonfet
674 *poly,xpc,allfets *poly,xpc,allfets
675#ifdef REDISTRIBUTION
676 # RDL connects to m5 (i.e., padl) through glass cut
677 *mrdl *mrdl
678 glass metrdl
679#endif (REDISTRIBUTION)
680end
681
682#-----------------------------------------------------
683# CIF/GDS output layer definitions
684#-----------------------------------------------------
685# NOTE: All values in this section MUST be multiples of 25
686# or else magic will scale below the allowed layout grid size
687
688cifoutput
689
690#----------------------------------------------------------------
691style gdsii
692# NOTE: This section is used for actual GDS output
693#----------------------------------------------------------------
694 scalefactor 10 nanometers
695 options calma-permissive-labels
696 gridlimit 5
697
698#----------------------------------------------------------------
699# Create a temp layer from the cell bounding box for use in
700# generating ID layers. Note that "boundary", unlike "bbox",
701# requires the FIXED_BBOX property (abutment box) in the cell.
702#----------------------------------------------------------------
703 templayer CELLBOUND
704 boundary
705
706#----------------------------------------------------------------
707# BOUND
708#----------------------------------------------------------------
709 layer BOUND CELLBOUND
710 calma 235 4
711
712# Create a boundary outside of an abutment box, so that layers
713# can be made to stretch to the abutment box edges. First strink
714# so that any box that would be so small as to interact with
715# itself will be removed.
716
717 templayer CELLRING CELLBOUND
718 shrink 345
719 grow 545
720 and-not CELLBOUND
721
722#----------------------------------------------------------------
723# DNWELL
724#----------------------------------------------------------------
725
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]726 layer DNWELL dnwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]727 calma 64 18
728
729 layer PWRES rpw
730 and dnwell
731 calma 64 13
732
733#----------------------------------------------------------------
734# NWELL
735#----------------------------------------------------------------
736
737 layer NWELL allnwell
738 bloat-all rpw dnwell
739 and-not rpw,pwell
740 calma 64 20
741
742 layer WELLTXT
743 labels allnwell noport
744 calma 64 16
745
746 layer WELLPIN
747 labels allnwell port
748 calma 64 5
749
750#----------------------------------------------------------------
751# SUB (text/port only)
752#----------------------------------------------------------------
753
754 layer SUBTXT
755 labels pwell noport
756 calma 122 16
757
758 layer SUBPIN
759 labels pwell port
760 calma 64 59
761
762#----------------------------------------------------------------
763# DIFF
764#----------------------------------------------------------------
765
766 layer DIFF allnactivenontap,allpactivenontap,allactiveres
767 labels allnactivenontap,allpactivenontap
768 calma 65 20
769
770#----------------------------------------------------------------
771# TAP
772#----------------------------------------------------------------
773
774 layer TAP allnactivetap,allpactivetap
775 labels allnactivetap,allpactivetap
776 calma 65 44
777
778#----------------------------------------------------------------
779# PPLUS, NPLUS (PSDM, NSDM)
780#----------------------------------------------------------------
781
782 templayer basePPLUS pdiffres,mvpdiffres
783 grow 15
784 or xhrpoly,uhrpoly,xpc
785 grow 110
786 bloat-or allpactivetap * 125 allnactivenontap 0
787 bloat-or allpactivenontap * 125 allnactivetap 0
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]788
789 templayer baseNPLUS ndiffres,mvndiffres
790 grow 125
791 bloat-or allnactivetap * 125 allpactivenontap 0
792 bloat-or allnactivenontap * 125 allpactivetap 0
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]793
794 templayer extendPPLUS basePPLUS,CELLRING
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]795 bridge 380 380
796 and-not baseNPLUS
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]797 and-not CELLRING
798
799 layer PPLUS basePPLUS,extendPPLUS
800 close 265000
801 calma 94 20
802
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]803 templayer extendNPLUS baseNPLUS,CELLRING
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]804 bridge 380 380
805 and-not basePPLUS
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]806 and-not CELLRING
807
808 layer NPLUS baseNPLUS,extendNPLUS
809 close 265000
810 calma 93 44
811
812#----------------------------------------------------------------
813# LVTN
814#----------------------------------------------------------------
815
816 layer LVTN pfetlvt,nfetlvt,mvvar,mvnnfet,nsonos,*pdiodelvt,*ndiodelvt,*nndiode
817 grow 180
818 bridge 380 380
819 grow 185
820 shrink 185
821 close 265000
822 calma 125 44
823
824#----------------------------------------------------------------
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]825# HVTR
826#----------------------------------------------------------------
827
828 layer HVTR pfetmvt
829 grow 180
830 bridge 380 380
831 grow 185
832 shrink 185
833 close 265000
834 calma 18 20
835
836#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]837# HVTP
838#----------------------------------------------------------------
839
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]840 layer HVTP scpfethvt,ppu,pfethvt,varhvt,*pdiodehvt
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]841 grow 180
842 bridge 380 380
843 grow 185
844 shrink 185
845 close 265000
846 calma 78 44
847
848#----------------------------------------------------------------
849# SONOS
850#----------------------------------------------------------------
851
852 layer SONOS nsonos
853 grow 100
854 grow-min 410
855 bridge 500 410
856 grow 250
857 shrink 250
858 calma 80 20
859
860#----------------------------------------------------------------
861# SONOS requires COREID around area (areaid.ce). Also, the
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]862# coreli layer indicates a cell needing COREID. Also, devices
863# npd, npass, and ppu indicate a COREID cell.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]864#----------------------------------------------------------------
865
866 layer COREID
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]867 bloat-all nsonos,coreli,ppu,npd,npass CELLBOUND
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]868 calma 81 2
869
870#----------------------------------------------------------------
871# STDCELL applies to all cells containing scnfet or scpfet.
872#----------------------------------------------------------------
873
874 layer STDCELL scnfet
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]875 bloat-all scpfet,scpfethvt,scnfet CELLBOUND
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]876 calma 81 4
877
878#----------------------------------------------------------------
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]879# NPNID and PNPID apply to bipolar transistors
880#----------------------------------------------------------------
881
882 layer NPNID
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]883 bloat-all npn dnwell
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]884 calma 82 20
885
886 templayer pnparea pnp
887 grow 400
888
889 layer PNPID
890 bloat-all pnparea *psd
891 or pnparea
892 calma 82 44
893
894#----------------------------------------------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]895# RPM
896#----------------------------------------------------------------
897
898 layer RPM
899 bloat-all xhrpoly xpc
900 grow 200
901 grow-min 1270
902 grow 420
903 shrink 420
904 calma 86 20
905
906#----------------------------------------------------------------
907# URPM (2kOhms/sq. poly implant)
908#----------------------------------------------------------------
909
910 layer URPM
911 bloat-all uhrpoly xpc
912 grow 200
913 grow-min 1270
914 grow 420
915 shrink 420
916 calma 79 20
917
918#----------------------------------------------------------------
919# LDNTM (Tip implant for SONOS FETs)
920#----------------------------------------------------------------
921
922 layer LDNTM
923 bloat-all nsonos *ndiff
924 grow 185
925 grow 345
926 shrink 345
927 calma 11 44
928
929#----------------------------------------------------------------
930# HVNTM (Tip implant for MV ndiff devices)
931#----------------------------------------------------------------
932
933 templayer hvntm_block *mvpsd
934 grow 185
935
936 layer HVNTM
937 bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
938 bloat-all mvvaractor *mvnsd
939 and-not hvntm_block
940 grow 185
941 grow 345
942 shrink 345
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]943 and-not hvntm_block
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]944 calma 125 20
945
946#----------------------------------------------------------------
947# POLY
948#----------------------------------------------------------------
949
950 layer POLY allpoly
951 calma 66 20
952
953 layer POLYTXT
954 labels allpoly noport
955 calma 66 16
956
957 layer POLYPIN
958 labels allpoly port
959 calma 66 5
960
961#----------------------------------------------------------------
962# THKOX (HVI) (includes rules NWELL 8-11 and DIFFTAP 14-26)
963#----------------------------------------------------------------
964
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]965 templayer thkox_area alldiffmv,mvvar
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]966 grow 185
Tim Edwardsab7cf0d2020-11-18 22:13:34 -0500[diff] [blame]967 bloat-all alldiffmv nwell
968 grow 345
969 shrink 345
970
971 templayer large_ptap_mv thkox_area
972 shrink 420
973 grow 420
974
975 templayer small_ptap_mv thkox_area
976 and-not large_ptap_mv
977 # (HVI min width rule is 0.6 but CNTM min width rule is 0.84um)
978 grow-min 840
979
980 templayer baseTHKOX thkox_area,small_ptap_mv
Tim Edwardseacb0a62020-11-17 20:20:13 -0500[diff] [blame]981 bridge 700 600
982 grow 345
983 shrink 345
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]984
985 templayer extendTHKOX baseTHKOX,CELLRING
986 grow 345
987 shrink 345
988 and-not CELLRING
989
990 layer THKOX baseTHKOX,extendTHKOX
991 calma 75 20
992
993#----------------------------------------------------------------
994# CONT (LICON)
995#----------------------------------------------------------------
996
997 layer CONT allcont
998 squares-grid 0 170 170
999 calma 66 44
1000
1001 # Contact for pres is different than other LICON contacts
1002 # See rules LICON 1b, 1c (width/length) and 2b (spacing)
1003 templayer xpc_horiz xpc
1004 shrink 1007
1005 grow 1007
1006
1007 layer CONT xpc
1008 and-not xpc_horiz
1009 # Force long edge vertical for contacts narrower than 2um
1010 # Minimum space is 350 but 520 satisfies no. of contacts rule
1011 slots 80 190 520 80 2000 350
1012 calma 66 44
1013
1014 layer CONT xpc
1015 and xpc_horiz
1016 # Force long edge vertical for contacts wider than 2um
1017 # Minimum space is 350 but 520 satisfies no. of contacts rule
1018 slots 80 2000 350 80 190 520
1019 calma 66 44
1020
1021#----------------------------------------------------------------
1022# NPC (Nitride poly cut)
1023# surrounds CONT (LICON) on poly only (i.e., pc)
1024#----------------------------------------------------------------
1025
1026 layer NPC pc
1027 squares-grid 0 170 170
1028 grow 100
1029 bridge 270 270
1030 grow 130
1031 shrink 130
1032 calma 95 20
1033
1034 # NPC is also generated on xhrpoly and uhrpoly resistors
1035
1036 layer NPC xpc,xhrpoly,uhrpoly
1037 # xpc surrounds precision_resistor by 0.095um
1038 grow 95
1039 grow 130
1040 shrink 130
1041 calma 95 20
1042
1043#----------------------------------------------------------------
1044# Device markers
1045#----------------------------------------------------------------
1046
1047 layer DIFFRES rdn,mvrdn,rdp,mvrdp
1048 calma 65 13
1049
1050 layer POLYRES mrp1
1051 calma 66 13
1052
1053 # POLYSHORT is a poly layer resistor like rli, rm1, etc., for metal layers
1054 layer POLYSHORT rmp
1055 calma 66 15
1056
1057 # POLYRES extends to edge of contact cut
1058 layer POLYRES xhrpoly,uhrpoly
1059 grow 60
1060 and xpc
1061 or xhrpoly,uhrpoly
1062 calma 66 13
1063
1064 layer DIODE *pdi,*ndi,*nndi,*mvpdi,*mvndi,*pdilvt,*pdihvt,*ndilvt
1065 # To be done: Expand to include anode, cathode, and guard ring
1066 calma 81 23
1067
1068#----------------------------------------------------------------
1069# LI
1070#----------------------------------------------------------------
1071 layer LI allli
1072 calma 67 20
1073
1074 layer LITXT
1075 labels *locali,coreli noport
1076 calma 67 16
1077
1078 layer LIPIN
1079 labels *locali,coreli port
1080 calma 67 5
1081
1082 layer LIRES rli
1083 labels rli
1084 calma 67 13
1085
1086#----------------------------------------------------------------
1087# MCON
1088#----------------------------------------------------------------
1089 layer MCON lic
1090 squares-grid 0 170 190
1091 calma 67 44
1092
1093#----------------------------------------------------------------
1094# MET1
1095#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1096 layer MET1 allm1,m1fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1097 calma 68 20
1098
1099 layer MET1TXT
1100 labels allm1 noport
1101 calma 68 16
1102
1103 layer MET1PIN
1104 labels allm1 port
1105 calma 68 5
1106
1107 layer MET1RES rm1
1108 labels rm1
1109 calma 68 13
1110
1111#----------------------------------------------------------------
1112# VIA1
1113#----------------------------------------------------------------
1114 layer VIA1 via1
1115 squares-grid 55 150 170
1116 calma 68 44
1117
1118#----------------------------------------------------------------
1119# MET2
1120#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1121 layer MET2 allm2,m2fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1122 calma 69 20
1123
1124 layer MET2TXT
1125 labels allm2 noport
1126 calma 69 16
1127
1128 layer MET2PIN
1129 labels allm2 port
1130 calma 69 5
1131
1132 layer MET2RES rm2
1133 labels rm2
1134 calma 69 13
1135
1136#----------------------------------------------------------------
1137# VIA2
1138#----------------------------------------------------------------
1139 layer VIA2 via2
1140 squares-grid 40 200 200
1141 calma 69 44
1142
1143#----------------------------------------------------------------
1144# MET3
1145#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1146 layer MET3 allm3,m3fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1147 calma 70 20
1148
1149 layer MET3TXT
1150 labels allm3 noport
1151 calma 70 16
1152
1153 layer MET3PIN
1154 labels allm3 port
1155 calma 70 5
1156
1157 layer MET3RES rm3
1158 labels rm3
1159 calma 70 13
1160
1161#ifdef METAL5
1162#----------------------------------------------------------------
1163# VIA3
1164#----------------------------------------------------------------
1165 layer VIA3 via3
1166#ifdef MIM
1167 or mimcc
1168#endif (MIM)
1169 squares-grid 60 200 200
1170 calma 70 44
1171
1172#----------------------------------------------------------------
1173# MET4
1174#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1175 layer MET4 allm4,m4fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1176 calma 71 20
1177
1178 layer MET4TXT
1179 labels allm4 noport
1180 calma 71 16
1181
1182 layer MET4PIN
1183 labels allm4 port
1184 calma 71 5
1185
1186 layer MET4RES rm4
1187 labels rm4
1188 calma 71 13
1189
1190#----------------------------------------------------------------
1191# VIA4
1192#----------------------------------------------------------------
1193 layer VIA4 via4
1194#ifdef MIM
1195 or mim2cc
1196#endif (MIM)
1197 squares-grid 190 800 800
1198 calma 71 44
1199
1200#----------------------------------------------------------------
1201# MET5
1202#----------------------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1203 layer MET5 allm5,m5fill
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1204 calma 72 20
1205
1206 layer MET5TXT
1207 labels allm5 noport
1208 calma 72 16
1209
1210 layer MET5PIN
1211 labels allm5 port
1212 calma 72 5
1213
1214 layer MET5RES rm5
1215 labels rm5
1216 calma 72 13
1217
1218#endif (METAL5)
1219
1220#ifdef REDISTRIBUTION
1221#----------------------------------------------------------------
1222# RDL
1223#----------------------------------------------------------------
1224 layer RDL *metrdl
1225 calma 74 20
1226
1227 layer RDLTXT
1228 labels *metrdl noport
1229 calma 74 16
1230
1231 layer RDLPIN
1232 labels *metrdl port
1233 calma 74 5
1234
Tim Edwardsfa35ae22020-10-21 10:59:05 -0400[diff] [blame]1235 layer PI1 *metrdl
1236 and padl,glass
1237 # Test only---needs GDS layer number
1238
1239 layer UBM *metrdl
1240 shrink 50000
1241 grow 40000
1242 # Test only---needs GDS layer number
1243
1244 layer PI2 *metrdl
1245 shrink 50000
1246 grow 25000
1247 # Test only---needs GDS layer number
1248
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1249#endif REDISTRIBUTION
1250
1251#----------------------------------------------------------------
1252# GLASS
1253#----------------------------------------------------------------
1254 layer GLASS glass
1255 calma 76 20
1256
1257#ifdef MIM
1258#----------------------------------------------------------------
1259# CAPM
1260#----------------------------------------------------------------
1261 layer CAPM *mimcap
1262 labels mimcap
1263 calma 89 44
1264
1265 layer CAPM2 *mimcap2
1266 labels mimcap2
1267 calma 97 44
1268#endif (MIM)
1269
1270#----------------------------------------------------------------
1271# Chip top level marker for DRC latchup rules to check 15um
1272# distance to taps (otherwise 6um is used)
1273#----------------------------------------------------------------
1274
1275 layer LOWTAPDENSITY
1276 bbox top
1277 # Clear 200um for pads + 50um for required high tap density
1278 # in critical area.
1279 shrink 250000
1280 calma 81 14
1281
1282#----------------------------------------------------------------
1283# FILLBLOCK
1284#----------------------------------------------------------------
1285 layer FILLOBSM1 fillblock
1286 calma 62 24
1287
1288 layer FILLOBSM2 fillblock
1289 calma 105 52
1290
1291 layer FILLOBSM3 fillblock
1292 calma 107 24
1293
1294 layer FILLOBSM4 fillblock
1295 calma 112 4
1296
1297 render DNWELL cwell -0.1 0.1
1298 render NWELL nwell 0.0 0.2062
1299 render DIFF ndiffusion 0.2062 0.12
1300 render TAP pdiffusion 0.2062 0.12
1301 render POLY polysilicon 0.3262 0.18
1302 render CONT via 0.5062 0.43
1303 render LI metal1 0.9361 0.10
1304 render MCON via 1.0361 0.34
1305 render MET1 metal2 1.3761 0.36
1306 render VIA1 via 1.7361 0.27
1307 render MET2 metal3 2.0061 0.36
1308 render VIA2 via 2.3661 0.42
1309 render MET3 metal4 2.7861 0.845
1310#ifdef METAL5
1311 render VIA3 via 3.6311 0.39
1312 render MET4 metal5 4.0211 0.845
1313 render VIA4 via 4.8661 0.505
1314 render MET5 metal6 5.3711 1.26
1315 render CAPM metal8 2.4661 0.2
1316 render CAPM2 metal9 3.7311 0.2
1317#ifdef REDISTRIBUTION
1318 render RDL metal7 11.8834 4.0
1319#endif (!REDISTRIBUTION)
1320#endif (!METAL5)
1321
1322#----------------------------------------------------------------
1323style drc
1324#----------------------------------------------------------------
1325# NOTE: This style is used for DRC only, not for GDS output
1326#----------------------------------------------------------------
1327 scalefactor 10 nanometers
1328 options calma-permissive-labels
1329
1330 # Ensure nwell overlaps dnwell at least 0.4um outside and 1.03um inside
1331 templayer dnwell_shrink dnwell
1332 shrink 1030
1333
1334 templayer nwell_missing dnwell
1335 grow 400
1336 and-not dnwell_shrink
1337 and-not nwell
1338
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1339 templayer pwell_in_dnwell dnwell
1340 and-not nwell
1341
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1342 # SONOS nFET devices must be in deep nwell
1343 templayer dnwell_missing nsonos
1344 and-not dnwell
1345
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1346 # SONOS nFET devices must be in cell with abutment box
1347 templayer abutment_box
1348 boundary
1349
1350 templayer bbox_missing nsonos
1351 and-not abutment_box
1352
1353 # Make sure nwell covers varactor poly
1354 templayer var_poly_no_nwell
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]1355 bloat-all varactor,mvvaractor *poly
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1356 grow 150
1357 and-not nwell
1358
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1359 # Define MiM cap bottom plate for spacing rule
1360 templayer mim_bottom
1361 bloat-all *mimcap *metal3
1362
1363 # Define MiM2 cap bottom plate for spacing rule
1364 templayer mim2_bottom
1365 bloat-all *mimcap2 *metal4
1366
1367 # Note that metal fill is performed by the foundry and so is not
1368 # an option for a cifoutput style.
1369
1370 # Check latchup rule (15um minimum from tap LICON center to any
1371 # non-tap diffusion. Note that to count as a tap, the diffusion
1372 # must be contacted to LI
1373
1374 templayer ptap_reach psc,mvpsc
1375 and-not dnwell
1376 # grow total is 15um. grow in 0.84um increments to ensure that
1377 # no nwell ring is crossed
1378 grow 840
1379 and-not nwell,dnwell
1380 grow 840
1381 and-not nwell,dnwell
1382 grow 840
1383 and-not nwell,dnwell
1384 grow 840
1385 and-not nwell,dnwell
1386 grow 840
1387 and-not nwell,dnwell
1388 grow 840
1389 and-not nwell,dnwell
1390 grow 840
1391 and-not nwell,dnwell
1392 grow 840
1393 and-not nwell,dnwell
1394 grow 840
1395 and-not nwell,dnwell
1396 grow 840
1397 and-not nwell,dnwell
1398 grow 840
1399 and-not nwell,dnwell
1400 grow 840
1401 and-not nwell,dnwell
1402 grow 840
1403 and-not nwell,dnwell
1404 grow 840
1405 and-not nwell,dnwell
1406 grow 840
1407 and-not nwell,dnwell
1408 grow 840
1409 and-not nwell,dnwell
1410 grow 840
1411 and-not nwell,dnwell
1412 grow 635
1413 and-not nwell,dnwell
1414
1415 templayer ptap_missing *ndiff,*mvndiff
1416 and-not dnwell
1417 and-not ptap_reach
1418
1419 templayer ntap_reach nsc,mvnsc
1420 # grow total is 15um. grow in 1.27um increments to ensure that
1421 # no nwell ring is crossed. There is no difference between
1422 # ntaps in and out of deep nwell.
1423 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1424 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1425 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1426 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1427 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1428 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1429 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1430 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1431 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1432 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1433 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1434 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1435 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1436 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1437 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1438 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1439 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1440 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1441 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1442 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1443 grow 1270
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1444 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1445 grow 945
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1446 and nwell,pnp
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1447
1448 templayer ntap_missing *pdiff,*mvpdiff
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1449 and-not pwell_in_dnwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1450 and-not ntap_reach
1451
1452 templayer dptap_reach psc,mvpsc
1453 and dnwell
1454 grow 840
1455 and-not nwell
1456 and dnwell
1457 grow 840
1458 and-not nwell
1459 and dnwell
1460 grow 840
1461 and-not nwell
1462 and dnwell
1463 grow 840
1464 and-not nwell
1465 and dnwell
1466 grow 840
1467 and-not nwell
1468 and dnwell
1469 grow 840
1470 and-not nwell
1471 and dnwell
1472 grow 840
1473 and-not nwell
1474 and dnwell
1475 grow 840
1476 and-not nwell
1477 and dnwell
1478 grow 840
1479 and-not nwell
1480 and dnwell
1481 grow 840
1482 and-not nwell
1483 and dnwell
1484 grow 840
1485 and-not nwell
1486 and dnwell
1487 grow 840
1488 and-not nwell
1489 and dnwell
1490 grow 840
1491 and-not nwell
1492 and dnwell
1493 grow 840
1494 and-not nwell
1495 and dnwell
1496 grow 840
1497 and-not nwell
1498 and dnwell
1499 grow 840
1500 and-not nwell
1501 and dnwell
1502 grow 840
1503 and-not nwell
1504 and dnwell
1505 grow 635
1506 and-not nwell
1507 and dnwell
1508
1509 templayer dptap_missing *ndiff,*mvndiff
1510 and dnwell
1511 and-not dptap_reach
1512
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]1513 templayer pdiff_crosses_dnwell dnwell
1514 grow 20
1515 and-not dnwell
1516 and allpdifflv,allpdiffmv
1517
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1518 # MV nwell must be 2um from any other nwell
1519 templayer mvnwell
1520 bloat-all alldiffmv nwell
1521 grow-min 840
1522 bridge 700 600
1523
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]1524 # Simple spacing checks to lvnwell must use CIF-DRC rule
1525 templayer allmvdiffnowell *mvndiff,*mvpsd
1526
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1527 templayer lvnwell nwell
1528 and-not mvnwell
1529
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1530 templayer nwell_with_tap
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1531 bloat-all nsc,mvnsc nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1532
Tim Edwards7d5c22f2020-11-20 15:12:13 -0500[diff] [blame]1533 templayer nwell_missing_tap nwell,pnp
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1534 and-not nwell_with_tap
1535
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]1536 templayer tap_with_licon
1537 bloat-all psc,mvpsc psd,mvpsd
1538 bloat-all nsc,mvnsc nsd,mvnsd
1539
1540 templayer tap_missing_licon psd,nsd,mvpsd,mvnsd
1541 and-not tap_with_licon
1542
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1543 # Make sure varactor nwell contains no P diffusion
1544 templayer pdiff_in_varactor_well
1545 bloat-all varactor,mvvaractor nwell
1546 and allpactive
1547
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]1548 # HVNTM spacing requires recreating HVNTM
1549 templayer hvntm_block *mvpsd
1550 grow 185
1551
1552 templayer hvntm_generate
1553 bloat-all mvnfet,mvnnfet,*mvndiode,mvrdn,*nndiode *mvndiff
1554 bloat-all mvvaractor *mvnsd
1555 and-not hvntm_block
1556 grow 185
1557 grow 345
1558 shrink 345
1559 and-not hvntm_block
1560
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1561 templayer m1_small_hole allm1,obsm1,obslic
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1562 close 140000
1563
1564 templayer m1_hole_empty m1_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1565 and-not allm1,obsm1,obslic
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1566
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1567 templayer m2_small_hole allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1568 close 140000
1569
1570 templayer m2_hole_empty m2_small_hole
Tim Edwards28cea2f2020-09-17 22:09:30 -0400[diff] [blame]1571 and-not allm2,obsm2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1572
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]1573 templayer m1_huge allm1
1574 shrink 1500
1575 grow 1500
1576
1577 templayer m1_large_halo m1_huge
1578 grow 280
1579 and-not m1_huge
1580 and allm1
1581
1582 templayer m2_huge allm2
1583 shrink 1500
1584 grow 1500
1585
1586 templayer m2_large_halo m2_huge
1587 grow 280
1588 and-not m2_huge
1589 and allm2
1590
1591 templayer m3_huge allm3
1592 shrink 1500
1593 grow 1500
1594
1595 templayer m3_large_halo m3_huge
1596 grow 400
1597 and-not m3_huge
1598 and allm3
1599
1600 templayer m4_huge allm4
1601 shrink 1500
1602 grow 1500
1603
1604 templayer m4_large_halo m4_huge
1605 grow 400
1606 and-not m4_huge
1607 and allm4
1608
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]1609#ifdef EXPERIMENTAL
1610#----------------------------------------------------------------
1611style paint
1612#----------------------------------------------------------------
1613# NOTE: This style is used for database manipulations only via
1614# the "cif paint" command.
1615#----------------------------------------------------------------
1616
1617 scalefactor 10 nanometers
1618
1619 templayer m1grow *m1
1620 grow 290
1621
1622 # layer listrap: Use the following set of commands to strap local
1623 # interconnect wires with metal1 (inside the cursor box) to satisfy
1624 # the maximum aspect ratio rule for local interconnect:
1625 #
1626 # tech unlock *
1627 # cif ostyle paint
1628 # cif paint m1strap comment
1629 # cif paint m1strap m1
1630 # cif paint listrap licon
1631 # erase comment
1632
1633 templayer m1strap *li
1634 and-not m1grow
1635 grow 30
1636
1637 templayer listrap comment
1638 slots 30 170 170 60
1639
1640#endif (EXPERIMENTAL)
1641
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1642#----------------------------------------------------------------
1643style wafflefill
1644#----------------------------------------------------------------
1645# Style used by scripts for automatically generating fill layers
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1646#----------------------------------------------------------------
1647 scalefactor 10 nanometers
1648 options calma-permissive-labels
1649 gridlimit 5
1650
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1651#----------------------------------------------------------------
1652# Generate guard-band around nwells to keep FOM from crossing
1653# Spacing from nwell = Diff/Tap 9 = 0.34um
1654# Enclosure by nwell = Diff/Tap 8 = 0.18um
1655#----------------------------------------------------------------
1656 templayer well_shrink nwell
1657 shrink 180
1658 templayer well_guardband nwell
1659 grow 340
1660 and-not well_shrink
1661
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1662#---------------------------------------------------
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1663# Interleaved FOM and POLY fill
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1664#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1665 templayer slots_fom_pass1
1666 bbox top
1667 slots 0 4080 1320 0 4080 1320 1360 0
1668 templayer obstruct_fom_pass1 alldiff,allpoly,rpw
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]1669 grow 500
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1670 or well_guardband
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1671 templayer fomfill_pass1 slots_fom_pass1
1672 and-not obstruct_fom_pass1
1673 shrink 2035
1674 grow 2035
1675
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1676#---------------------------------------------------
1677
1678 templayer slots_poly_pass1
1679 bbox top
1680 slots 0 720 360 0 720 360 240 0
1681 templayer obstruct_poly_pass1 alldiff,allpoly,rpw
1682 grow 700
1683 or fomfill_pass1
1684 grow 300
1685 or well_guardband
1686 templayer polyfill_pass1 slots_poly_pass1
1687 and-not obstruct_poly_pass1
1688 shrink 355
1689 grow 355
1690
1691#---------------------------------------------------
1692
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1693 templayer slots_fom_pass2
1694 bbox top
1695 slots 0 2500 1320 0 2500 1320 1360 0
1696 templayer obstruct_fom_pass2 fomfill_pass1
1697 grow 820
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1698 grow 200
1699 or polyfill_pass1
1700 grow 300
1701 or obstruct_fom_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1702 templayer fomfill_pass2 slots_fom_pass2
1703 and-not obstruct_fom_pass2
1704 shrink 1245
1705 grow 1245
1706
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1707#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1708
1709 templayer slots_poly_coarse
1710 bbox top
1711 slots 0 720 360 0 720 360 240 120
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1712 templayer obstruct_poly_coarse polyfill_pass1
1713 grow 60
1714 or fomfill_pass1,fomfill_pass2
1715 grow 300
1716 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1717 templayer polyfill_coarse slots_poly_coarse
1718 and-not obstruct_poly_coarse
1719 shrink 355
1720 grow 355
1721
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1722#---------------------------------------------------
1723
1724 templayer slots_fom_coarse
1725 bbox top
1726 slots 0 1500 1320 0 1500 1320 1360 0
1727 templayer obstruct_fom_coarse fomfill_pass1,fomfill_pass2
1728 grow 1020
1729 or polyfill_pass1,polyfill_coarse
1730 grow 300
1731 or obstruct_fom_pass1
1732 templayer fomfill_coarse slots_fom_coarse
1733 and-not obstruct_fom_coarse
1734 shrink 745
1735 grow 745
1736
1737#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1738 templayer slots_poly_medium
1739 bbox top
1740 slots 0 540 360 0 540 360 240 100
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1741 templayer obstruct_poly_medium polyfill_pass1,polyfill_coarse
1742 grow 1010
1743 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1744 templayer polyfill_medium slots_poly_medium
1745 and-not obstruct_poly_medium
1746 shrink 265
1747 grow 265
1748
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1749#---------------------------------------------------
1750
1751 templayer slots_fom_fine
1752 bbox top
1753 slots 0 500 400 0 500 400 160 0
1754 templayer obstruct_fom_fine fomfill_pass1,fomfill_pass2,fomfill_coarse
1755 grow 1320
1756 or obstruct_fom_pass1
1757 templayer fomfill_fine slots_fom_fine
1758 and-not obstruct_fom_fine
1759 shrink 245
1760 grow 245
1761
1762#---------------------------------------------------
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1763 templayer slots_poly_fine
1764 bbox top
1765 slots 0 480 360 0 480 360 240 200
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1766 templayer obstruct_poly_fine polyfill_pass1,polyfill_coarse,polyfill_medium
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1767 grow 650
1768 or polyfill_pass1,polyfill_coarse,polyfill_medium
1769 grow 360
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1770 or obstruct_poly_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1771 templayer polyfill_fine slots_poly_fine
1772 and-not obstruct_poly_fine
1773 shrink 235
1774 grow 235
1775
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1776#---------------------------------------------------
1777 templayer fomfill fomfill_pass1
1778 or fomfill_pass2
1779 or fomfill_coarse
1780 or fomfill_fine
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1781
1782 templayer polyfill polyfill_pass1
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1783 or polyfill_coarse
1784 or polyfill_medium
1785 or polyfill_fine
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1786
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1787 layer FOMMASK fomfill
Tim Edwards475b5272020-08-25 14:05:50 -0400[diff] [blame]1788 calma 23 0
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1789 layer POLYMASK polyfill
Tim Edwards475b5272020-08-25 14:05:50 -0400[diff] [blame]1790 calma 28 0
Tim Edwards7ac1f032020-08-12 17:40:36 -0400[diff] [blame]1791
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]1792#---------------------------------------------------
1793# MET1 fill
1794#---------------------------------------------------
1795 templayer slots_m1_coarse
1796 bbox top
1797 slots 0 2000 200 0 2000 200 700 0
1798 templayer obstruct_m1_coarse allm1,allpad,obsm1,m1fill,fillblock
1799 grow 3000
1800 templayer met1fill_coarse slots_m1_coarse
1801 and-not obstruct_m1_coarse
1802 shrink 995
1803 grow 995
1804
1805 templayer slots_m1_medium
1806 bbox top
1807 slots 0 1000 200 0 1000 200 700 0
1808 templayer obstruct_m1_medium allm1,allpad,obsm1,m1fill,fillblock
1809 grow 2800
1810 or met1fill_coarse
1811 grow 200
1812 templayer met1fill_medium slots_m1_medium
1813 and-not obstruct_m1_medium
1814 shrink 495
1815 grow 495
1816
1817 templayer slots_m1_fine
1818 bbox top
1819 slots 0 580 200 0 580 200 700 0
1820 templayer obstruct_m1_fine allm1,allpad,obsm1,m1fill,fillblock
1821 grow 300
1822 or met1fill_coarse,met1fill_medium
1823 grow 200
1824 templayer met1fill_fine slots_m1_fine
1825 and-not obstruct_m1_fine
1826 shrink 285
1827 grow 285
1828
1829 templayer slots_m1_veryfine
1830 bbox top
1831 slots 0 300 200 0 300 200 100 50
1832 templayer obstruct_m1_veryfine allm1,allpad,obsm1,m1fill,fillblock
1833 grow 100
1834 or met1fill_coarse,met1fill_medium,met1fill_fine
1835 grow 200
1836 templayer met1fill_veryfine slots_m1_veryfine
1837 and-not obstruct_m1_veryfine
1838 shrink 145
1839 grow 145
1840
1841 layer MET1MASK met1fill_coarse
1842 or met1fill_medium
1843 or met1fill_fine
1844 or met1fill_veryfine
1845 calma 36 0
1846
1847#---------------------------------------------------
1848# MET2 fill
1849#---------------------------------------------------
1850 templayer slots_m2_coarse
1851 bbox top
1852 slots 0 2000 200 0 2000 200 700 350
1853 templayer obstruct_m2 allm2,allpad,obsm2,m2fill,fillblock
1854 grow 3000
1855 templayer met2fill_coarse slots_m2_coarse
1856 and-not obstruct_m2
1857 shrink 995
1858 grow 995
1859
1860 templayer slots_m2_medium
1861 bbox top
1862 slots 0 1000 200 0 1000 200 700 350
1863 templayer obstruct_m2_medium allm2,allpad,obsm2,m2fill,fillblock
1864 grow 2800
1865 or met2fill_coarse
1866 grow 200
1867 templayer met2fill_medium slots_m2_medium
1868 and-not obstruct_m2_medium
1869 shrink 495
1870 grow 495
1871
1872 templayer slots_m2_fine
1873 bbox top
1874 slots 0 580 200 0 580 200 700 350
1875 templayer obstruct_m2_fine allm2,allpad,obsm2,m2fill,fillblock
1876 grow 300
1877 or met2fill_coarse,met2fill_medium
1878 grow 200
1879 templayer met2fill_fine slots_m2_fine
1880 and-not obstruct_m2_fine
1881 shrink 285
1882 grow 285
1883
1884 templayer slots_m2_veryfine
1885 bbox top
1886 slots 0 300 200 0 300 200 100 100
1887 templayer obstruct_m2_veryfine allm2,allpad,obsm2,m2fill,fillblock
1888 grow 100
1889 or met2fill_coarse,met2fill_medium,met2fill_fine
1890 grow 200
1891 templayer met2fill_veryfine slots_m2_veryfine
1892 and-not obstruct_m2_veryfine
1893 shrink 145
1894 grow 145
1895
1896 layer MET2MASK met2fill_coarse
1897 or met2fill_medium
1898 or met2fill_fine
1899 or met2fill_veryfine
1900 calma 41 0
1901
1902#---------------------------------------------------
1903# MET3 fill
1904#---------------------------------------------------
1905 templayer slots_m3_coarse
1906 bbox top
1907 slots 0 2000 300 0 2000 300 700 700
1908 templayer obstruct_m3 allm3,allpad,obsm3,m3fill,fillblock
1909 grow 3000
1910 templayer met3fill_coarse slots_m3_coarse
1911 and-not obstruct_m3
1912 shrink 995
1913 grow 995
1914
1915 templayer slots_m3_medium
1916 bbox top
1917 slots 0 1000 300 0 1000 300 700 700
1918 templayer obstruct_m3_medium allm3,allpad,obsm3,m3fill,fillblock
1919 grow 2700
1920 or met3fill_coarse
1921 grow 300
1922 templayer met3fill_medium slots_m3_medium
1923 and-not obstruct_m3_medium
1924 shrink 495
1925 grow 495
1926
1927 templayer slots_m3_fine
1928 bbox top
1929 slots 0 580 300 0 580 300 700 700
1930 templayer obstruct_m3_fine allm3,allpad,obsm3,m3fill,fillblock
1931 grow 200
1932 or met3fill_coarse,met3fill_medium
1933 grow 300
1934 templayer met3fill_fine slots_m3_fine
1935 and-not obstruct_m3_fine
1936 shrink 285
1937 grow 285
1938
1939 templayer slots_m3_veryfine
1940 bbox top
1941 slots 0 400 300 0 400 300 150 200
1942 templayer obstruct_m3_veryfine allm3,allpad,obsm3,m3fill,fillblock
1943 or met3fill_coarse,met3fill_medium,met3fill_fine
1944 grow 300
1945 templayer met3fill_veryfine slots_m3_veryfine
1946 and-not obstruct_m3_veryfine
1947 shrink 195
1948 grow 195
1949
1950 layer MET3MASK met3fill_coarse
1951 or met3fill_medium
1952 or met3fill_fine
1953 or met3fill_veryfine
1954 calma 34 0
1955
1956#ifdef METAL5
1957#---------------------------------------------------
1958# MET4 fill
1959#---------------------------------------------------
1960 templayer slots_m4_coarse
1961 bbox top
1962 slots 0 2000 300 0 2000 300 700 1050
1963 templayer obstruct_m4 allm4,allpad,obsm4,m4fill,fillblock
1964 grow 3000
1965 templayer met4fill_coarse slots_m4_coarse
1966 and-not obstruct_m4
1967 shrink 995
1968 grow 995
1969
1970 templayer slots_m4_medium
1971 bbox top
1972 slots 0 1000 300 0 1000 300 700 1050
1973 templayer obstruct_m4_medium allm4,allpad,obsm4,m4fill,fillblock
1974 grow 2700
1975 or met4fill_coarse
1976 grow 300
1977 templayer met4fill_medium slots_m4_medium
1978 and-not obstruct_m4_medium
1979 shrink 495
1980 grow 495
1981
1982 templayer slots_m4_fine
1983 bbox top
1984 slots 0 580 300 0 580 300 700 1050
1985 templayer obstruct_m4_fine allm4,allpad,obsm4,m4fill,fillblock
1986 grow 200
1987 or met4fill_coarse,met4fill_medium
1988 grow 300
1989 templayer met4fill_fine slots_m4_fine
1990 and-not obstruct_m4_fine
1991 shrink 285
1992 grow 285
1993
1994 templayer slots_m4_veryfine
1995 bbox top
1996 slots 0 400 300 0 400 300 150 300
1997 templayer obstruct_m4_veryfine allm4,allpad,obsm4,m4fill,fillblock
1998 or met4fill_coarse,met4fill_medium,met4fill_fine
1999 grow 300
2000 templayer met4fill_veryfine slots_m4_veryfine
2001 and-not obstruct_m4_veryfine
2002 shrink 195
2003 grow 195
2004
2005 layer MET4MASK met4fill_coarse
2006 or met4fill_medium
2007 or met4fill_fine
2008 or met4fill_veryfine
2009 calma 51 0
2010
2011#---------------------------------------------------
2012# MET5 fill
2013#---------------------------------------------------
2014 templayer slots_m5
2015 bbox top
2016 slots 0 3000 1600 0 3000 1600 1000 100
2017 templayer obstruct_m5 allm5,allpad,obsm5,m5fill,fillblock
2018 grow 3000
2019 templayer met5fill_gen slots_m5
2020 and-not obstruct_m5
2021 shrink 1495
2022 grow 1495
2023
2024 layer MET5MASK met5fill_gen
2025 calma 59 0
2026#endif (METAL5)
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2027
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2028end
2029
2030#-----------------------------------------------------------------------
2031cifinput
2032#-----------------------------------------------------------------------
2033# NOTE: All values in this section MUST be multiples of 25
2034# or else magic will scale below the allowed layout grid size
2035#-----------------------------------------------------------------------
2036
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]2037style sky130
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2038 scalefactor 10 nanometers
2039 gridlimit 5
2040
2041 options ignore-unknown-layer-labels no-reconnect-labels
2042
2043#ifndef MIM
2044 ignore CAPM
2045 ignore CAPM2
2046#endif (!MIM)
2047#ifndef METAL5
2048 ignore MET4,VIA3
2049 ignore MET5,VIA4
2050#endif
2051 ignore NPC
2052 ignore SEALID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2053 ignore CAPID
2054 ignore LDNTM
2055 ignore HVNTM
2056 ignore POLYMOD
2057 ignore LOWTAPDENSITY
2058
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2059 layer pnp NWELL,WELLTXT,WELLPIN
2060 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2061 labels NWELL
2062 labels WELLTXT text
2063 labels WELLPIN port
2064
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2065 layer nwell NWELL,WELLTXT,WELLPIN
2066 and-not PNPID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2067 labels NWELL
2068 labels WELLTXT text
2069 labels WELLPIN port
2070
2071 layer pwell SUBTXT,SUBPIN
2072 labels SUBTXT text
2073 labels SUBPIN port
2074
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]2075 # Always draw pwell under p-tap
2076 layer pwell TAP
2077 and-not NWELL
2078
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2079 layer dnwell DNWELL
2080 labels DNWELL
2081
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]2082 layer npn DNWELL
2083 and-not NWELL
2084 and NPNID
2085
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2086 layer rpw PWRES
2087 and DNWELL
2088 labels PWRES
2089
2090 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
2091 and-not POLY
2092 and-not NWELL
2093 and-not PPLUS
2094 and-not DIODE
2095 and-not DIFFRES
2096 and-not THKOX
2097 and NPLUS
2098 copyup ndifcheck
2099 labels DIFF
2100 labels DIFFTXT text
2101 labels DIFFPIN port
2102 labels TAPPIN port
2103
2104 layer ndiff ndiffarea
2105
2106 # Copy ndiff areas up for contact checks
2107 templayer xndifcheck ndifcheck
2108 copyup ndifcheck
2109
2110 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
2111 and-not POLY
2112 and-not NWELL
2113 and-not PPLUS
2114 and-not DIODE
2115 and-not DIFFRES
2116 and THKOX
2117 and NPLUS
2118 copyup ndifcheck
2119 labels DIFF
2120 labels DIFFTXT text
2121 labels DIFFPIN port
2122
2123 layer mvndiff mvndiffarea
2124
2125 # Copy ndiff areas up for contact checks
2126 templayer mvxndifcheck mvndifcheck
2127 copyup mvndifcheck
2128
2129 layer ndiode DIFF
2130 and NPLUS
2131 and DIODE
2132 and-not NWELL
2133 and-not POLY
2134 and-not PPLUS
2135 and-not THKOX
2136 and-not LVTN
2137 labels DIFF
2138
2139 layer ndiodelvt DIFF
2140 and NPLUS
2141 and DIODE
2142 and-not NWELL
2143 and-not POLY
2144 and-not PPLUS
2145 and-not THKOX
2146 and LVTN
2147 labels DIFF
2148
2149 templayer ndiodearea DIODE
2150 and NPLUS
2151 and-not THKOX
2152 and-not NWELL
2153 copyup DIODE,NPLUS
2154
2155 layer ndiffres DIFFRES
2156 and NPLUS
2157 and-not THKOX
2158 labels DIFF
2159
2160 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
2161 and-not POLY
2162 and NWELL
2163 and-not NPLUS
2164 and-not DIODE
2165 and-not THKOX
2166 and PPLUS
2167 copyup pdifcheck
2168 labels DIFF
2169 labels DIFFTXT text
2170 labels DIFFPIN port
2171
2172 layer pdiff pdiffarea
2173
2174 layer mvndiode DIFF
2175 and NPLUS
2176 and DIODE
2177 and THKOX
2178 and-not POLY
2179 and-not PPLUS
2180 and-not LVTN
2181 labels DIFF
2182
2183 layer nndiode DIFF
2184 and NPLUS
2185 and DIODE
2186 and THKOX
2187 and-not POLY
2188 and-not PPLUS
2189 and LVTN
2190 labels DIFF
2191
2192 templayer mvndiodearea DIODE
2193 and NPLUS
2194 and THKOX
2195 and-not NWELL
2196 copyup DIODE,NPLUS
2197
2198 layer mvndiffres DIFFRES
2199 and NPLUS
2200 and THKOX
2201 labels DIFF
2202
2203 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
2204 and-not POLY
2205 and NWELL
2206 and-not NPLUS
2207 and THKOX
2208 and-not DIODE
2209 and-not DIFFRES
2210 and PPLUS
2211 copyup mvpdifcheck
2212 labels DIFF
2213 labels DIFFTXT text
2214 labels DIFFPIN port
2215
2216 layer mvpdiff mvpdiffarea
2217
2218 # Copy pdiff areas up for contact checks
2219 templayer xpdifcheck pdifcheck
2220 copyup pdifcheck
2221
2222 layer pdiode DIFF
2223 and PPLUS
2224 and-not POLY
2225 and-not NPLUS
2226 and-not THKOX
2227 and-not LVTN
2228 and-not HVTP
2229 and DIODE
2230 labels DIFF
2231
2232 layer pdiodelvt DIFF
2233 and PPLUS
2234 and-not POLY
2235 and-not NPLUS
2236 and-not THKOX
2237 and LVTN
2238 and-not HVTP
2239 and DIODE
2240 labels DIFF
2241
2242 layer pdiodehvt DIFF
2243 and PPLUS
2244 and-not POLY
2245 and-not NPLUS
2246 and-not THKOX
2247 and-not LVTN
2248 and HVTP
2249 and DIODE
2250 labels DIFF
2251
2252 templayer pdiodearea DIODE
2253 and PPLUS
2254 and-not THKOX
2255 copyup DIODE,PPLUS
2256
2257 # Define pfet areas as known pdiff, regardless of the presence of a well.
2258
2259 templayer pfetarea DIFF
2260 and-not NPLUS
2261 and-not THKOX
2262 and POLY
2263
2264 layer pfet pfetarea
2265 and-not LVTN
2266 and-not HVTP
2267 and-not STDCELL
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2268 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2269 labels DIFF
2270
2271 layer scpfet pfetarea
2272 and-not LVTN
2273 and-not HVTP
2274 and STDCELL
2275 labels DIFF
2276
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2277 layer scpfethvt pfetarea
2278 and-not LVTN
2279 and HVTP
2280 and STDCELL
2281 labels DIFF
2282
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2283 layer ppu pfetarea
2284 and-not LVTN
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2285 and HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2286 and COREID
2287 labels DIFF
2288
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2289 layer pfetlvt pfetarea
2290 and LVTN
2291 labels DIFF
2292
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]2293 layer pfetmvt pfetarea
2294 and HVTR
2295 labels DIFF
2296
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2297 layer pfethvt pfetarea
2298 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2299 and-not STDCELL
Tim Edwards0747adc2020-11-13 19:19:00 -0500[diff] [blame]2300 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2301 labels DIFF
2302
2303 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
2304 layer nwell pfetarea
2305 grow 180
2306
2307 # Copy mvpdiff areas up for contact checks
2308 templayer mvxpdifcheck mvpdifcheck
2309 copyup mvpdifcheck
2310
2311 layer mvpdiode DIFF
2312 and PPLUS
2313 and-not POLY
2314 and-not NPLUS
2315 and THKOX
2316 and DIODE
2317 labels DIFF
2318
2319 templayer mvpdiodearea DIODE
2320 and PPLUS
2321 and THKOX
2322 copyup DIODE,PPLUS
2323
2324 # Define pfet areas as known pdiff,
2325 # regardless of the presence of a
2326 # well.
2327
2328 templayer mvpfetarea DIFF
2329 and-not NPLUS
2330 and THKOX
2331 and POLY
2332
2333 layer mvpfet mvpfetarea
2334 labels DIFF
2335
2336 layer pdiff DIFF,DIFFTXT,DIFFPIN
2337 and-not NPLUS
2338 and-not POLY
2339 and-not THKOX
2340 and-not DIODE
2341 and-not DIFFRES
2342 labels DIFF
2343 labels DIFFTXT text
2344 labels DIFFPIN port
2345
2346 layer pdiffres DIFFRES
2347 and PPLUS
2348 and NWELL
2349 and-not THKOX
2350 labels DIFF
2351
2352 layer nfet DIFF
2353 and POLY
2354 and-not PPLUS
2355 and NPLUS
2356 and-not THKOX
2357 and-not LVTN
2358 and-not SONOS
2359 and-not STDCELL
2360 labels DIFF
2361
2362 layer scnfet DIFF
2363 and POLY
2364 and-not PPLUS
2365 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2366 and-not NWELL
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2367 and-not THKOX
2368 and-not LVTN
2369 and-not SONOS
2370 and STDCELL
2371 labels DIFF
2372
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2373 layer npass DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2374 and POLY
2375 and-not PPLUS
2376 and NPLUS
2377 and-not NWELL
2378 and COREID
2379 labels DIFF
2380
Tim Edwards8d30fd32020-11-13 19:31:20 -0500[diff] [blame]2381 layer npd DIFF
2382 and POLY
2383 and-not PPLUS
2384 and NPLUS
2385 and-not NWELL
2386 and COREID
2387 # Shrink-grow operation eliminates the smaller npass device
2388 shrink 70
2389 grow 70
2390 labels DIFF
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2391
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2392 layer nfetlvt DIFF
2393 and POLY
2394 and-not PPLUS
2395 and NPLUS
2396 and-not THKOX
2397 and LVTN
2398 and-not SONOS
2399 labels DIFF
2400
2401 layer nsonos DIFF
2402 and POLY
2403 and-not PPLUS
2404 and NPLUS
2405 and-not THKOX
2406 and LVTN
2407 and SONOS
2408 labels DIFF
2409
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2410 templayer nsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2411 and NPLUS
2412 and NWELL
2413 and-not POLY
2414 and-not PPLUS
2415 and-not THKOX
2416 copyup nsubcheck
2417
2418 layer nsd nsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2419 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2420
2421 layer nsd TAP,TAPPIN
2422 and NPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2423 and-not POLY
2424 and-not THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2425 labels TAP
2426 labels TAPPIN port
2427
2428 templayer nsdexpand nsdarea
2429 grow 500
2430
2431 # Copy nsub areas up for contact checks
2432 templayer xnsubcheck nsubcheck
2433 copyup nsubcheck
2434
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2435 templayer psdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2436 and PPLUS
2437 and-not NWELL
2438 and-not POLY
2439 and-not NPLUS
2440 and-not THKOX
2441 and-not pfetexpand
2442 copyup psubcheck
2443
2444 layer psd psdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2445 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2446
2447 layer psd TAP,TAPPIN
2448 and PPLUS
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2449 and-not POLY
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2450 and-not THKOX
2451 labels TAP
2452 labels TAPPIN port
2453
2454 templayer psdexpand psdarea
2455 grow 500
2456
2457 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
2458 and-not NPLUS
2459 and-not POLY
2460 and THKOX
2461 and mvpfetexpand
2462 labels DIFF
2463 labels DIFFTXT text
2464 labels DIFFPIN port
2465
2466 layer mvpdiffres DIFFRES
2467 and PPLUS
2468 and NWELL
2469 and THKOX
2470 and-not mvrdpioedge
2471 labels DIFF
2472
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2473 templayer mvnfetarea DIFF
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2474 and POLY
2475 and-not PPLUS
2476 and NPLUS
2477 and-not LVTN
2478 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2479 grow 1000
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2480
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2481 templayer mvnnfetarea DIFF,TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2482 and POLY
2483 and-not PPLUS
2484 and NPLUS
2485 and LVTN
2486 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]2487 and-not mvnfetarea
2488
2489 layer mvnfet DIFF
2490 and POLY
2491 and-not PPLUS
2492 and NPLUS
2493 and THKOX
2494 and-not mvnnfetarea
2495 labels DIFF
2496
2497 layer mvnnfet mvnnfetarea
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2498 labels DIFF
2499
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2500 templayer mvnsdarea TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2501 and NPLUS
2502 and NWELL
2503 and-not POLY
2504 and-not PPLUS
2505 and THKOX
2506 copyup mvnsubcheck
2507
2508 layer mvnsd mvnsdarea
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2509 labels TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2510
2511 layer mvnsd TAP,TAPPIN
2512 and NPLUS
2513 and THKOX
2514 labels TAP
2515 labels TAPPIN port
2516
2517 templayer mvnsdexpand mvnsdarea
2518 grow 500
2519
2520 # Copy nsub areas up for contact checks
2521 templayer mvxnsubcheck mvnsubcheck
2522 copyup mvnsubcheck
2523
2524 templayer mvpsdarea DIFF
2525 and PPLUS
2526 and-not NWELL
2527 and-not POLY
2528 and-not NPLUS
2529 and THKOX
2530 and-not mvpfetexpand
2531 copyup mvpsubcheck
2532
2533 layer mvpsd mvpsdarea
2534 labels DIFF
2535
2536 layer mvpsd TAP,TAPPIN
2537 and PPLUS
2538 and THKOX
2539 labels TAP
2540 labels TAPPIN port
2541
2542 templayer mvpsdexpand mvpsdarea
2543 grow 500
2544
2545 # Copy psub areas up for contact checks
2546 templayer xpsubcheck psubcheck
2547 copyup psubcheck
2548
2549 templayer mvxpsubcheck mvpsubcheck
2550 copyup mvpsubcheck
2551
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2552 layer psd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2553 and-not PPLUS
2554 and-not NPLUS
2555 and-not POLY
2556 and-not THKOX
2557 and-not pfetexpand
2558 and psdexpand
2559
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2560 layer nsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2561 and-not PPLUS
2562 and-not NPLUS
2563 and-not POLY
2564 and-not THKOX
2565 and nsdexpand
2566
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2567 layer mvpsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2568 and-not PPLUS
2569 and-not NPLUS
2570 and-not POLY
2571 and THKOX
2572 and-not mvpfetexpand
2573 and mvpsdexpand
2574
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]2575 layer mvnsd TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2576 and-not PPLUS
2577 and-not NPLUS
2578 and-not POLY
2579 and THKOX
2580 and mvnsdexpand
2581
2582 templayer hresarea POLY
2583 and RPM
2584 grow 3000
2585
2586 templayer uresarea POLY
2587 and URPM
2588 grow 3000
2589
2590 templayer diffresarea DIFFRES
2591 and-not THKOX
2592 grow 3000
2593
2594 templayer mvdiffresarea DIFFRES
2595 and THKOX
2596 grow 3000
2597
2598 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
2599
2600 layer pfet POLY
2601 and DIFF
2602 and diffresarea
2603 and-not NPLUS
2604 and-not STDCELL
2605
2606 layer scpfet POLY
2607 and DIFF
2608 and diffresarea
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]2609 and-not HVTP
2610 and-not NPLUS
2611 and STDCELL
2612
2613 layer scpfethvt POLY
2614 and DIFF
2615 and diffresarea
2616 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2617 and-not NPLUS
2618 and STDCELL
2619
2620 templayer xpolyterm RPM,URPM
2621 and POLY
2622 and-not POLYRES
2623 # add back the 0.06um contact surround in the direction of the resistor
2624 grow 60
2625 and POLY
2626
2627 layer xpc xpolyterm
2628
2629 templayer polyarea POLY
2630 and-not POLYRES
2631 and-not POLYSHORT
2632 and-not DIFF
2633 and-not RPM
2634 and-not URPM
2635 copyup polycheck
2636
2637 layer poly polyarea,POLYTXT,POLYPIN
2638 labels POLY
2639 labels POLYTXT text
2640 labels POLYPIN port
2641
2642 # Copy (non-resistor) poly areas up for contact checks
2643 templayer xpolycheck polycheck
2644 copyup polycheck
2645
2646 layer mrp1 POLY
2647 and POLYRES
2648 and-not RPM
2649 and-not URPM
2650 labels POLY
2651
2652 layer rmp POLY
2653 and POLYSHORT
2654 labels POLY
2655
2656 layer xhrpoly POLY
2657 and POLYRES
2658 and RPM
2659 and-not URPM
2660 and PPLUS
2661 and NPC
2662 and-not xpolyterm
2663 labels POLY
2664
2665 layer uhrpoly POLY
2666 and POLYRES
2667 and URPM
2668 and-not RPM
2669 and NPC
2670 and-not xpolyterm
2671 labels POLY
2672
2673 templayer ndcbase CONT
2674 and DIFF
2675 and NPLUS
2676 and-not NWELL
2677 and LI
2678 and-not THKOX
2679
2680 layer ndc ndcbase
2681 grow 85
2682 shrink 85
2683 shrink 85
2684 grow 85
2685 or ndcbase
2686 labels CONT
2687
2688 templayer nscbase CONT
2689 and DIFF,TAP
2690 and NPLUS
2691 and NWELL
2692 and LI
2693 and-not THKOX
2694
2695 layer nsc nscbase
2696 grow 85
2697 shrink 85
2698 shrink 85
2699 grow 85
2700 or nscbase
2701 labels CONT
2702
2703 templayer pdcbase CONT
2704 and DIFF
2705 and PPLUS
2706 and NWELL
2707 and LI
2708 and-not THKOX
2709
2710 layer pdc pdcbase
2711 grow 85
2712 shrink 85
2713 shrink 85
2714 grow 85
2715 or pdcbase
2716 labels CONT
2717
2718 templayer pdcnowell CONT
2719 and DIFF
2720 and PPLUS
2721 and pfetexpand
2722 and LI
2723 and-not THKOX
2724
2725 layer pdc pdcnowell
2726 grow 85
2727 shrink 85
2728 shrink 85
2729 grow 85
2730 or pdcnowell
2731 labels CONT
2732
2733 templayer pscbase CONT
2734 and DIFF,TAP
2735 and PPLUS
2736 and-not NWELL
2737 and-not pfetexpand
2738 and LI
2739 and-not THKOX
2740
2741 layer psc pscbase
2742 grow 85
2743 shrink 85
2744 shrink 85
2745 grow 85
2746 or pscbase
2747 labels CONT
2748
2749 templayer pcbase CONT
2750 and POLY
2751 and-not DIFF
2752 and-not RPM,URPM
2753 and LI
2754
2755 layer pc pcbase
2756 grow 85
2757 shrink 85
2758 shrink 85
2759 grow 85
2760 or pcbase
2761 labels CONT
2762
2763 templayer ndicbase CONT
2764 and DIFF
2765 and NPLUS
2766 and DIODE
2767 and-not POLY
2768 and-not PPLUS
2769 and-not THKOX
2770 and-not LVTN
2771
2772 layer ndic ndicbase
2773 grow 85
2774 shrink 85
2775 shrink 85
2776 grow 85
2777 or ndicbase
2778 labels CONT
2779
2780 templayer ndilvtcbase CONT
2781 and DIFF
2782 and NPLUS
2783 and DIODE
2784 and-not POLY
2785 and-not PPLUS
2786 and-not THKOX
2787 and LVTN
2788
2789 layer ndilvtc ndilvtcbase
2790 grow 85
2791 shrink 85
2792 shrink 85
2793 grow 85
2794 or ndilvtcbase
2795 labels CONT
2796
2797 templayer pdicbase CONT
2798 and DIFF
2799 and PPLUS
2800 and DIODE
2801 and-not POLY
2802 and-not NPLUS
2803 and-not THKOX
2804 and-not LVTN
2805 and-not HVTP
2806
2807 layer pdic pdicbase
2808 grow 85
2809 shrink 85
2810 shrink 85
2811 grow 85
2812 or pdicbase
2813 labels CONT
2814
2815 templayer pdilvtcbase CONT
2816 and DIFF
2817 and PPLUS
2818 and DIODE
2819 and-not POLY
2820 and-not NPLUS
2821 and-not THKOX
2822 and LVTN
2823 and-not HVTP
2824
2825 layer pdilvtc pdilvtcbase
2826 grow 85
2827 shrink 85
2828 shrink 85
2829 grow 85
2830 or pdilvtcbase
2831 labels CONT
2832
2833 templayer pdihvtcbase CONT
2834 and DIFF
2835 and PPLUS
2836 and DIODE
2837 and-not POLY
2838 and-not NPLUS
2839 and-not THKOX
2840 and-not LVTN
2841 and HVTP
2842
2843 layer pdihvtc pdihvtcbase
2844 grow 85
2845 shrink 85
2846 shrink 85
2847 grow 85
2848 or pdihvtcbase
2849 labels CONT
2850
2851 templayer mvndcbase CONT
2852 and DIFF
2853 and NPLUS
2854 and-not NWELL
2855 and LI
2856 and THKOX
2857
2858 layer mvndc mvndcbase
2859 grow 85
2860 shrink 85
2861 shrink 85
2862 grow 85
2863 or mvndcbase
2864 labels CONT
2865
2866 templayer mvnscbase CONT
2867 and DIFF,TAP
2868 and NPLUS
2869 and NWELL
2870 and LI
2871 and THKOX
2872
2873 layer mvnsc mvnscbase
2874 grow 85
2875 shrink 85
2876 shrink 85
2877 grow 85
2878 or mvnscbase
2879 labels CONT
2880
2881 templayer mvpdcbase CONT
2882 and DIFF
2883 and PPLUS
2884 and NWELL
2885 and LI
2886 and THKOX
2887
2888 layer mvpdc mvpdcbase
2889 grow 85
2890 shrink 85
2891 shrink 85
2892 grow 85
2893 or mvpdcbase
2894 labels CONT
2895
2896 templayer mvpdcnowell CONT
2897 and DIFF
2898 and PPLUS
2899 and mvpfetexpand
2900 and MET1
2901 and THKOX
2902
2903 layer mvpdc mvpdcnowell
2904 grow 85
2905 shrink 85
2906 shrink 85
2907 grow 85
2908 or mvpdcnowell
2909 labels CONT
2910
2911 templayer mvpscbase CONT
2912 and DIFF,TAP
2913 and PPLUS
2914 and-not NWELL
2915 and-not mvpfetexpand
2916 and LI
2917 and THKOX
2918
2919 layer mvpsc mvpscbase
2920 grow 85
2921 shrink 85
2922 shrink 85
2923 grow 85
2924 or mvpscbase
2925 labels CONT
2926
2927 templayer mvndicbase CONT
2928 and DIFF
2929 and NPLUS
2930 and DIODE
2931 and-not POLY
2932 and-not PPLUS
2933 and-not LVTN
2934 and THKOX
2935
2936 layer mvndic mvndicbase
2937 grow 85
2938 shrink 85
2939 shrink 85
2940 grow 85
2941 or mvndicbase
2942 labels CONT
2943
2944 templayer nndicbase CONT
2945 and DIFF
2946 and NPLUS
2947 and DIODE
2948 and-not POLY
2949 and-not PPLUS
2950 and LVTN
2951 and THKOX
2952
2953 layer nndic nndicbase
2954 grow 85
2955 shrink 85
2956 shrink 85
2957 grow 85
2958 or nndicbase
2959 labels CONT
2960
2961 templayer mvpdicbase CONT
2962 and DIFF
2963 and PPLUS
2964 and DIODE
2965 and-not POLY
2966 and-not NPLUS
2967 and THKOX
2968
2969 layer mvpdic mvpdicbase
2970 grow 85
2971 shrink 85
2972 shrink 85
2973 grow 85
2974 or mvpdicbase
2975 labels CONT
2976
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2977 layer coreli LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2978 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2979 and COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2980 labels LI
2981 labels LITXT text
2982 labels LIPIN port
2983
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2984 layer locali LI,LITXT,LIPIN
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2985 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]2986 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]2987 labels LI
2988 labels LITXT text
2989 labels LIPIN port
2990
2991 layer rli LI
2992 and LIRES,LISHORT
2993 labels LIRES,LISHORT
2994
2995 layer lic MCON
2996 grow 95
2997 shrink 95
2998 shrink 85
2999 grow 85
3000 or MCON
3001 labels MCON
3002
3003 layer m1 MET1,MET1TXT,MET1PIN
3004 and-not MET1RES,MET1SHORT
3005 labels MET1
3006 labels MET1TXT text
3007 labels MET1PIN port
3008
3009 layer rm1 MET1
3010 and MET1RES,MET1SHORT
3011 labels MET1RES,MET1SHORT
3012
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3013 layer m1fill MET1FILL
3014 labels MET1FILL
3015
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3016#ifdef MIM
3017 layer mimcap MET3
3018 and CAPM
3019 labels CAPM
3020
3021 layer mimcc VIA3
3022 and CAPM
3023 grow 60
3024 grow 40
3025 shrink 40
3026 labels CAPM
3027
3028 layer mimcap2 MET4
3029 and CAPM2
3030 labels CAPM2
3031
3032 layer mim2cc VIA4
3033 and CAPM2
3034 grow 190
3035 grow 210
3036 shrink 210
3037 labels CAPM2
3038
3039#endif (MIM)
3040
3041 templayer m2cbase VIA1
3042 grow 55
3043
3044 layer m2c m2cbase
3045 grow 30
3046 shrink 30
3047 shrink 130
3048 grow 130
3049 or m2cbase
3050
3051 layer m2 MET2,MET2TXT,MET2PIN
3052 and-not MET2RES,MET2SHORT
3053 labels MET2
3054 labels MET2TXT text
3055 labels MET2PIN port
3056
3057 layer rm2 MET2
3058 and MET2RES,MET2SHORT
3059 labels MET2RES,MET2SHORT
3060
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3061 layer m2fill MET2FILL
3062 labels MET2FILL
3063
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3064 templayer m3cbase VIA2
3065 grow 40
3066
3067 layer m3c m3cbase
3068 grow 60
3069 shrink 60
3070 shrink 140
3071 grow 140
3072 or m3cbase
3073
3074 layer m3 MET3,MET3TXT,MET3PIN
3075 and-not MET3RES,MET3SHORT
3076#ifdef MIM
3077 and-not CAPM
3078#endif (MIM)
3079 labels MET3
3080 labels MET3TXT text
3081 labels MET3PIN port
3082
3083 layer rm3 MET3
3084 and MET3RES,MET3SHORT
3085 labels MET3RES,MET3SHORT
3086
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3087 layer m3fill MET3FILL
3088 labels MET3FILL
3089
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3090#ifdef (METAL5)
3091
3092 templayer via3base VIA3
3093#ifdef MIM
3094 and-not CAPM
3095#endif (MIM)
3096 grow 60
3097
3098 layer via3 via3base
3099 grow 40
3100 shrink 40
3101 shrink 160
3102 grow 160
3103 or via3base
3104
3105 layer m4 MET4,MET4TXT,MET4PIN
3106 and-not MET4RES,MET4SHORT
3107#ifdef MIM
3108 and-not CAPM2
3109#endif (MIM)
3110 labels MET4
3111 labels MET4TXT text
3112 labels MET4PIN port
3113
3114 layer rm4 MET4
3115 and MET4RES,MET4SHORT
3116 labels MET4RES,MET4SHORT
3117
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3118 layer m4fill MET4FILL
3119 labels MET4FILL
3120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3121 layer m5 MET5,MET5TXT,MET5PIN
3122 and-not MET5RES,MET5SHORT
3123 labels MET5
3124 labels MET5TXT text
3125 labels MET5PIN port
3126
3127 layer rm5 MET5
3128 and MET5RES,MET5SHORT
3129 labels MET5RES,MET5SHORT
3130
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3131 layer m5fill MET5FILL
3132 labels MET5FILL
3133
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3134 templayer via4base VIA4
3135#ifdef MIM
3136 and-not CAPM2
3137#endif (MIM)
3138 grow 190
3139
3140 layer via4 via4base
3141 grow 210
3142 shrink 210
3143 shrink 590
3144 grow 590
3145 or via4base
3146#endif (METAL5)
3147
3148#ifdef REDISTRIBUTION
3149 layer metrdl RDL,RDLTXT,RDLPIN
3150 labels RDL
3151 labels RDLTXT text
3152 labels RDLPIN port
3153#endif
3154
3155 # Find diffusion not covered in
3156 # NPLUS or PPLUS and pull it into
3157 # the next layer up
3158
3159 templayer gentrans DIFF
3160 and-not PPLUS
3161 and-not NPLUS
3162 and POLY
3163 copyup DIFF,POLY
3164
3165 templayer gendiff DIFF,TAP
3166 and-not PPLUS
3167 and-not NPLUS
3168 and-not POLY
3169 copyup DIFF
3170
3171 # Handle contacts found by copyup
3172
3173 templayer ndiccopy CONT
3174 and LI
3175 and DIODE
3176 and NPLUS
3177 and-not THKOX
3178
3179 layer ndic ndiccopy
3180 grow 85
3181 shrink 85
3182 shrink 85
3183 grow 85
3184 or ndiccopy
3185 labels CONT
3186
3187 templayer mvndiccopy CONT
3188 and LI
3189 and DIODE
3190 and NPLUS
3191 and THKOX
3192
3193 layer mvndic mvndiccopy
3194 grow 85
3195 shrink 85
3196 shrink 85
3197 grow 85
3198 or mvndiccopy
3199 labels CONT
3200
3201 templayer pdiccopy CONT
3202 and LI
3203 and DIODE
3204 and PPLUS
3205 and-not THKOX
3206
3207 layer pdic pdiccopy
3208 grow 85
3209 shrink 85
3210 shrink 85
3211 grow 85
3212 or pdiccopy
3213 labels CONT
3214
3215 templayer mvpdiccopy CONT
3216 and LI
3217 and DIODE
3218 and PPLUS
3219 and THKOX
3220
3221 layer mvpdic mvpdiccopy
3222 grow 85
3223 shrink 85
3224 shrink 85
3225 grow 85
3226 or mvpdiccopy
3227 labels CONT
3228
3229 templayer ndccopy CONT
3230 and ndifcheck
3231
3232 layer ndc ndccopy
3233 grow 85
3234 shrink 85
3235 shrink 85
3236 grow 85
3237 or ndccopy
3238 labels CONT
3239
3240 templayer mvndccopy CONT
3241 and mvndifcheck
3242
3243 layer mvndc mvndccopy
3244 grow 85
3245 shrink 85
3246 shrink 85
3247 grow 85
3248 or mvndccopy
3249 labels CONT
3250
3251 templayer pdccopy CONT
3252 and pdifcheck
3253
3254 layer pdc pdccopy
3255 grow 85
3256 shrink 85
3257 shrink 85
3258 grow 85
3259 or pdccopy
3260 labels CONT
3261
3262 templayer mvpdccopy CONT
3263 and mvpdifcheck
3264
3265 layer mvpdc mvpdccopy
3266 grow 85
3267 shrink 85
3268 shrink 85
3269 grow 85
3270 or mvpdccopy
3271 labels CONT
3272
3273 templayer pccopy CONT
3274 and polycheck
3275
3276 layer pc pccopy
3277 grow 85
3278 shrink 85
3279 shrink 85
3280 grow 85
3281 or pccopy
3282 labels CONT
3283
3284 templayer nsccopy CONT
3285 and nsubcheck
3286
3287 layer nsc nsccopy
3288 grow 85
3289 shrink 85
3290 shrink 85
3291 grow 85
3292 or nsccopy
3293 labels CONT
3294
3295 templayer mvnsccopy CONT
3296 and mvnsubcheck
3297
3298 layer mvnsc mvnsccopy
3299 grow 85
3300 shrink 85
3301 shrink 85
3302 grow 85
3303 or mvnsccopy
3304 labels CONT
3305
3306 templayer psccopy CONT
3307 and psubcheck
3308
3309 layer psc psccopy
3310 grow 85
3311 shrink 85
3312 shrink 85
3313 grow 85
3314 or psccopy
3315 labels CONT
3316
3317 templayer mvpsccopy CONT
3318 and mvpsubcheck
3319
3320 layer mvpsc mvpsccopy
3321 grow 85
3322 shrink 85
3323 shrink 85
3324 grow 85
3325 or mvpsccopy
3326 labels CONT
3327
3328 # Find contacts not covered in
3329 # metal and pull them into the
3330 # next layer up
3331
3332 templayer gencont CONT
3333 and LI
3334 and-not DIFF,TAP
3335 and-not POLY
3336 and-not DIODE
3337 and-not nsubcheck
3338 and-not psubcheck
3339 and-not mvnsubcheck
3340 and-not mvpsubcheck
3341 copyup CONT,LI
3342
3343 templayer barecont CONT
3344 and-not LI
3345 and-not nsubcheck
3346 and-not psubcheck
3347 and-not mvnsubcheck
3348 and-not mvpsubcheck
3349 copyup CONT
3350
3351 layer glass GLASS,PADTXT,PADPIN
3352 labels GLASS
3353 labels PADTXT text
3354 labels PADPIN port
3355
3356 templayer boundary BOUND,STDCELL,PADCELL
3357 boundary
3358
3359 layer comment LVSTEXT
3360 labels LVSTEXT text
3361
3362 layer comment TTEXT
3363 labels TTEXT text
3364
3365 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3366 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
3367
3368# MOS Varactor
3369
3370 layer var POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3371 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3372 and NPLUS
3373 and NWELL
3374 and-not THKOX
3375 and-not HVTP
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3376 # NOTE: Else forms a varactor that is not in the vendor netlist.
3377 and-not COREID
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3378 labels POLY
3379
3380 layer varhvt POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3381 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3382 and NPLUS
3383 and NWELL
3384 and-not THKOX
3385 and HVTP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3386 labels POLY
3387
3388 layer mvvar POLY
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]3389 and TAP
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3390 and NPLUS
3391 and NWELL
3392 and THKOX
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3393 labels POLY
3394
3395 calma NWELL 64 20
3396 calma DIFF 65 20
3397 calma DNWELL 64 18
3398 calma PWRES 64 13
3399 calma TAP 65 44
3400 # LVTN
3401 calma LVTN 125 44
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]3402 # HVTR
3403 calma HVTR 18 20
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3404 # HVTP
3405 calma HVTP 78 44
3406 # SONOS (TUNM)
3407 calma SONOS 80 20
3408 # NPLUS = NSDM
3409 calma NPLUS 93 44
3410 # PPLUS = PSDM
3411 calma PPLUS 94 20
3412 # HVI
3413 calma THKOX 75 20
3414 # NPC
3415 calma NPC 95 20
3416 # P+ POLY MASK
3417 calma RPM 86 20
3418 calma URPM 79 20
3419 calma LDNTM 11 44
3420 calma HVNTM 125 20
Tim Edwards3af6a1e2020-09-16 11:48:17 -0400[diff] [blame]3421 # Poly resistor ID mark
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3422 calma POLYRES 66 13
3423 # Diffusion resistor ID mark
3424 calma DIFFRES 65 13
3425 calma POLY 66 20
3426 calma POLYMOD 66 83
3427 # Diode ID mark
3428 calma DIODE 81 23
3429 # Bipolar NPN mark
3430 calma NPNID 82 20
3431 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3432 calma PNPID 82 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3433 # Capacitor ID
3434 calma CAPID 82 64
3435 # Core area ID mark
3436 calma COREID 81 2
3437 # Standard cell ID mark
3438 calma STDCELL 81 4
3439 # Padframe cell ID mark
3440 calma PADCELL 81 3
3441 # Seal ring ID mark
3442 calma SEALID 81 1
3443 # Low tap density ID mark
3444 calma LOWTAPDENSITY 81 14
3445
3446 # LICON
3447 calma CONT 66 44
3448 calma LI 67 20
3449 calma MCON 67 44
3450
3451 calma MET1 68 20
3452 calma VIA1 68 44
3453 calma MET2 69 20
3454 calma VIA2 69 44
3455 calma MET3 70 20
3456#ifdef METAL5
3457 calma VIA3 70 44
3458 calma MET4 71 20
3459 calma VIA4 71 44
3460 calma MET5 72 20
3461#endif
3462#ifdef REDISTRIBUTION
3463 calma RDL 74 20
3464#endif
3465 calma GLASS 76 20
3466
3467 calma SUBPIN 64 59
3468 calma PADPIN 76 5
3469 calma DIFFPIN 65 6
3470 calma TAPPIN 65 5
3471 calma WELLPIN 64 5
3472 calma LIPIN 67 5
3473 calma POLYPIN 66 5
3474 calma MET1PIN 68 5
3475 calma MET2PIN 69 5
3476 calma MET3PIN 70 5
3477#ifdef METAL5
3478 calma MET4PIN 71 5
3479 calma MET5PIN 72 5
3480#endif
3481#ifdef REDISTRIBUTION
3482 calma RDLPIN 74 5
3483#endif
3484
3485 calma LIRES 67 13
3486 calma MET1RES 68 13
3487 calma MET2RES 69 13
3488 calma MET3RES 70 13
3489#ifdef METAL5
3490 calma MET4RES 71 13
3491 calma MET5RES 72 13
3492#endif
3493
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]3494 calma MET1FILL 68 28
3495 calma MET2FILL 69 28
3496 calma MET3FILL 70 28
3497#ifdef METAL5
3498 calma MET4FILL 71 28
3499 calma MET5FILL 72 28
3500#endif
3501
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]3502 calma POLYSHORT 66 15
3503 calma LISHORT 67 15
3504 calma MET1SHORT 68 15
3505 calma MET2SHORT 69 15
3506 calma MET3SHORT 70 15
3507#ifdef METAL5
3508 calma MET4SHORT 71 15
3509 calma MET5SHORT 72 15
3510#endif
3511
3512 calma SUBTXT 122 16
3513 calma PADTXT 76 16
3514 calma DIFFTXT 65 16
3515 calma POLYTXT 66 16
3516 calma WELLTXT 64 16
3517 calma LITXT 67 16
3518 calma MET1TXT 68 16
3519 calma MET2TXT 69 16
3520 calma MET3TXT 70 16
3521#ifdef METAL5
3522 calma MET4TXT 71 16
3523 calma MET5TXT 72 16
3524#endif
3525#ifdef REDISTRIBUTION
3526 calma RDLPIN 74 16
3527#endif
3528
3529 calma BOUND 235 4
3530
3531 calma LVSTEXT 83 44
3532
3533#ifdef (MIM)
3534 calma CAPM 89 44
3535 calma CAPM2 97 44
3536#endif (MIM)
3537
3538 calma FILLOBSM1 62 24
3539 calma FILLOBSM2 105 52
3540 calma FILLOBSM3 107 24
3541 calma FILLOBSM4 112 4
3542
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3543#-----------------------------------------------------------------------
3544
3545style vendorimport
3546 scalefactor 10 nanometers
3547 gridlimit 5
3548
3549 options ignore-unknown-layer-labels no-reconnect-labels
3550
3551#ifndef MIM
3552 ignore CAPM
3553 ignore CAPM2
3554#endif (!MIM)
3555#ifndef METAL5
3556 ignore MET4,VIA3
3557 ignore MET5,VIA4
3558#endif
3559 ignore NPC
3560 ignore SEALID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3561 ignore CAPID
3562 ignore LDNTM
3563 ignore HVNTM
3564 ignore POLYMOD
3565 ignore LOWTAPDENSITY
3566
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3567 layer pnp NWELL,WELLTXT,WELLPIN
3568 and PNPID
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3569 labels NWELL
3570 labels WELLTXT port
3571 labels WELLPIN port
3572
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]3573 layer nwell NWELL,WELLTXT,WELLPIN
3574 and-not PNPID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3575 labels NWELL
3576 labels WELLTXT port
3577 labels WELLPIN port
3578
3579 layer pwell SUBTXT,SUBPIN
3580 labels SUBTXT port
3581 labels SUBPIN port
3582
Tim Edwardsbb30e322020-10-07 16:51:21 -0400[diff] [blame]3583 # Always draw pwell under p-tap
3584 layer pwell TAP
3585 and-not NWELL
3586
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3587 layer dnwell DNWELL
3588 labels DNWELL
3589
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]3590 layer npn DNWELL
3591 and-not NWELL
3592 and NPNID
3593
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3594 layer rpw PWRES
3595 and DNWELL
3596 labels PWRES
3597
3598 templayer ndiffarea DIFF,DIFFTXT,DIFFPIN
3599 and-not POLY
3600 and-not NWELL
3601 and-not PPLUS
3602 and-not DIODE
3603 and-not DIFFRES
3604 and-not THKOX
3605 and NPLUS
3606 copyup ndifcheck
3607 labels DIFF
3608 labels DIFFTXT port
3609 labels DIFFPIN port
3610 labels TAPPIN port
3611
3612 layer ndiff ndiffarea
3613
3614 # Copy ndiff areas up for contact checks
3615 templayer xndifcheck ndifcheck
3616 copyup ndifcheck
3617
3618 templayer mvndiffarea DIFF,DIFFTXT,DIFFPIN
3619 and-not POLY
3620 and-not NWELL
3621 and-not PPLUS
3622 and-not DIODE
3623 and-not DIFFRES
3624 and THKOX
3625 and NPLUS
3626 copyup ndifcheck
3627 labels DIFF
3628 labels DIFFTXT port
3629 labels DIFFPIN port
3630
3631 layer mvndiff mvndiffarea
3632
3633 # Copy ndiff areas up for contact checks
3634 templayer mvxndifcheck mvndifcheck
3635 copyup mvndifcheck
3636
3637 layer ndiode DIFF
3638 and NPLUS
3639 and DIODE
3640 and-not NWELL
3641 and-not POLY
3642 and-not PPLUS
3643 and-not THKOX
3644 and-not LVTN
3645 labels DIFF
3646
3647 layer ndiodelvt DIFF
3648 and NPLUS
3649 and DIODE
3650 and-not NWELL
3651 and-not POLY
3652 and-not PPLUS
3653 and-not THKOX
3654 and LVTN
3655 labels DIFF
3656
3657 templayer ndiodearea DIODE
3658 and NPLUS
3659 and-not THKOX
3660 and-not NWELL
3661 copyup DIODE,NPLUS
3662
3663 layer ndiffres DIFFRES
3664 and NPLUS
3665 and-not THKOX
3666 labels DIFF
3667
3668 templayer pdiffarea DIFF,DIFFTXT,DIFFPIN
3669 and-not POLY
3670 and NWELL
3671 and-not NPLUS
3672 and-not DIODE
3673 and-not THKOX
3674 and PPLUS
3675 copyup pdifcheck
3676 labels DIFF
3677 labels DIFFTXT port
3678 labels DIFFPIN port
3679
3680 layer pdiff pdiffarea
3681
3682 layer mvndiode DIFF
3683 and NPLUS
3684 and DIODE
3685 and THKOX
3686 and-not POLY
3687 and-not PPLUS
3688 and-not LVTN
3689 labels DIFF
3690
3691 layer nndiode DIFF
3692 and NPLUS
3693 and DIODE
3694 and THKOX
3695 and-not POLY
3696 and-not PPLUS
3697 and LVTN
3698 labels DIFF
3699
3700 templayer mvndiodearea DIODE
3701 and NPLUS
3702 and THKOX
3703 and-not NWELL
3704 copyup DIODE,NPLUS
3705
3706 layer mvndiffres DIFFRES
3707 and NPLUS
3708 and THKOX
3709 labels DIFF
3710
3711 templayer mvpdiffarea DIFF,DIFFTXT,DIFFPIN
3712 and-not POLY
3713 and NWELL
3714 and-not NPLUS
3715 and THKOX
3716 and-not DIODE
3717 and-not DIFFRES
3718 and PPLUS
3719 copyup mvpdifcheck
3720 labels DIFF
3721 labels DIFFTXT port
3722 labels DIFFPIN port
3723
3724 layer mvpdiff mvpdiffarea
3725
3726 # Copy pdiff areas up for contact checks
3727 templayer xpdifcheck pdifcheck
3728 copyup pdifcheck
3729
3730 layer pdiode DIFF
3731 and PPLUS
3732 and-not POLY
3733 and-not NPLUS
3734 and-not THKOX
3735 and-not LVTN
3736 and-not HVTP
3737 and DIODE
3738 labels DIFF
3739
3740 layer pdiodelvt DIFF
3741 and PPLUS
3742 and-not POLY
3743 and-not NPLUS
3744 and-not THKOX
3745 and LVTN
3746 and-not HVTP
3747 and DIODE
3748 labels DIFF
3749
3750 layer pdiodehvt DIFF
3751 and PPLUS
3752 and-not POLY
3753 and-not NPLUS
3754 and-not THKOX
3755 and-not LVTN
3756 and HVTP
3757 and DIODE
3758 labels DIFF
3759
3760 templayer pdiodearea DIODE
3761 and PPLUS
3762 and-not THKOX
3763 copyup DIODE,PPLUS
3764
3765 # Define pfet areas as known pdiff, regardless of the presence of a well.
3766
3767 templayer pfetarea DIFF
3768 and-not NPLUS
3769 and-not THKOX
3770 and POLY
3771
3772 layer pfet pfetarea
3773 and-not LVTN
3774 and-not HVTP
3775 and-not STDCELL
3776 and-not COREID
3777 labels DIFF
3778
3779 layer scpfet pfetarea
3780 and-not LVTN
3781 and-not HVTP
3782 and STDCELL
3783 labels DIFF
3784
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3785 layer scpfethvt pfetarea
3786 and-not LVTN
3787 and HVTP
3788 and STDCELL
3789 labels DIFF
3790
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3791 layer ppu pfetarea
3792 and-not LVTN
Tim Edwards94513d42020-11-15 22:07:34 -0500[diff] [blame]3793 and HVTP
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3794 and COREID
3795 labels DIFF
3796
3797 layer pfetlvt pfetarea
3798 and LVTN
3799 labels DIFF
3800
3801 layer pfetmvt pfetarea
3802 and HVTR
3803 labels DIFF
3804
3805 layer pfethvt pfetarea
3806 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]3807 and-not STDCELL
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]3808 and-not COREID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3809 labels DIFF
3810
3811 # Always force nwell under pfet (nwell encloses pdiff by 0.18)
3812 layer nwell pfetarea
3813 grow 180
3814
3815 # Copy mvpdiff areas up for contact checks
3816 templayer mvxpdifcheck mvpdifcheck
3817 copyup mvpdifcheck
3818
3819 layer mvpdiode DIFF
3820 and PPLUS
3821 and-not POLY
3822 and-not NPLUS
3823 and THKOX
3824 and DIODE
3825 labels DIFF
3826
3827 templayer mvpdiodearea DIODE
3828 and PPLUS
3829 and THKOX
3830 copyup DIODE,PPLUS
3831
3832 # Define pfet areas as known pdiff,
3833 # regardless of the presence of a
3834 # well.
3835
3836 templayer mvpfetarea DIFF
3837 and-not NPLUS
3838 and THKOX
3839 and POLY
3840
3841 layer mvpfet mvpfetarea
3842 labels DIFF
3843
3844 layer pdiff DIFF,DIFFTXT,DIFFPIN
3845 and-not NPLUS
3846 and-not POLY
3847 and-not THKOX
3848 and-not DIODE
3849 and-not DIFFRES
3850 labels DIFF
3851 labels DIFFTXT port
3852 labels DIFFPIN port
3853
3854 layer pdiffres DIFFRES
3855 and PPLUS
3856 and NWELL
3857 and-not THKOX
3858 labels DIFF
3859
3860 layer nfet DIFF
3861 and POLY
3862 and-not PPLUS
3863 and NPLUS
3864 and-not THKOX
3865 and-not LVTN
3866 and-not SONOS
3867 and-not STDCELL
3868 labels DIFF
3869
3870 layer scnfet DIFF
3871 and POLY
3872 and-not PPLUS
3873 and NPLUS
3874 and-not NWELL
3875 and-not THKOX
3876 and-not LVTN
3877 and-not SONOS
3878 and STDCELL
3879 labels DIFF
3880
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]3881 layer npass DIFF
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3882 and POLY
3883 and-not PPLUS
3884 and NPLUS
3885 and-not NWELL
3886 and COREID
3887 labels DIFF
3888
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]3889 layer npd DIFF
3890 and POLY
3891 and-not PPLUS
3892 and NPLUS
3893 and-not NWELL
3894 and COREID
3895 # Shrink-grow operation eliminates the smaller npass device
3896 shrink 70
3897 grow 70
3898 labels DIFF
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3899
3900 layer nfetlvt DIFF
3901 and POLY
3902 and-not PPLUS
3903 and NPLUS
3904 and-not THKOX
3905 and LVTN
3906 and-not SONOS
3907 labels DIFF
3908
3909 layer nsonos DIFF
3910 and POLY
3911 and-not PPLUS
3912 and NPLUS
3913 and-not THKOX
3914 and LVTN
3915 and SONOS
3916 labels DIFF
3917
3918 templayer nsdarea TAP
3919 and NPLUS
3920 and NWELL
3921 and-not POLY
3922 and-not PPLUS
3923 and-not THKOX
3924 copyup nsubcheck
3925
3926 layer nsd nsdarea
3927 labels TAP
3928
3929 layer nsd TAP,TAPPIN
3930 and NPLUS
3931 and-not POLY
3932 and-not THKOX
3933 labels TAP
3934 labels TAPPIN port
3935
3936 templayer nsdexpand nsdarea
3937 grow 500
3938
3939 # Copy nsub areas up for contact checks
3940 templayer xnsubcheck nsubcheck
3941 copyup nsubcheck
3942
3943 templayer psdarea TAP
3944 and PPLUS
3945 and-not NWELL
3946 and-not POLY
3947 and-not NPLUS
3948 and-not THKOX
3949 and-not pfetexpand
3950 copyup psubcheck
3951
3952 layer psd psdarea
3953 labels TAP
3954
3955 layer psd TAP,TAPPIN
3956 and PPLUS
3957 and-not POLY
3958 and-not THKOX
3959 labels TAP
3960 labels TAPPIN port
3961
3962 templayer psdexpand psdarea
3963 grow 500
3964
3965 layer mvpdiff DIFF,DIFFTXT,DIFFPIN
3966 and-not NPLUS
3967 and-not POLY
3968 and THKOX
3969 and mvpfetexpand
3970 labels DIFF
3971 labels DIFFTXT port
3972 labels DIFFPIN port
3973
3974 layer mvpdiffres DIFFRES
3975 and PPLUS
3976 and NWELL
3977 and THKOX
3978 and-not mvrdpioedge
3979 labels DIFF
3980
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3981 templayer mvnfetarea DIFF
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3982 and POLY
3983 and-not PPLUS
3984 and NPLUS
3985 and-not LVTN
3986 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3987 grow 1000
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3988
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3989 templayer mvnnfetarea DIFF,TAP
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]3990 and POLY
3991 and-not PPLUS
3992 and NPLUS
3993 and LVTN
3994 and THKOX
Tim Edwards769d3622020-09-09 13:48:45 -0400[diff] [blame]3995 and-not mvnfetarea
3996
3997 layer mvnfet DIFF
3998 and POLY
3999 and-not PPLUS
4000 and NPLUS
4001 and THKOX
4002 and-not mvnnfetarea
4003 labels DIFF
4004
4005 layer mvnnfet mvnnfetarea
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4006 labels DIFF
4007
4008 templayer mvnsdarea TAP
4009 and NPLUS
4010 and NWELL
4011 and-not POLY
4012 and-not PPLUS
4013 and THKOX
4014 copyup mvnsubcheck
4015
4016 layer mvnsd mvnsdarea
4017 labels TAP
4018
4019 layer mvnsd TAP,TAPPIN
4020 and NPLUS
4021 and THKOX
4022 labels TAP
4023 labels TAPPIN port
4024
4025 templayer mvnsdexpand mvnsdarea
4026 grow 500
4027
4028 # Copy nsub areas up for contact checks
4029 templayer mvxnsubcheck mvnsubcheck
4030 copyup mvnsubcheck
4031
4032 templayer mvpsdarea DIFF
4033 and PPLUS
4034 and-not NWELL
4035 and-not POLY
4036 and-not NPLUS
4037 and THKOX
4038 and-not mvpfetexpand
4039 copyup mvpsubcheck
4040
4041 layer mvpsd mvpsdarea
4042 labels DIFF
4043
4044 layer mvpsd TAP,TAPPIN
4045 and PPLUS
4046 and THKOX
4047 labels TAP
4048 labels TAPPIN port
4049
4050 templayer mvpsdexpand mvpsdarea
4051 grow 500
4052
4053 # Copy psub areas up for contact checks
4054 templayer xpsubcheck psubcheck
4055 copyup psubcheck
4056
4057 templayer mvxpsubcheck mvpsubcheck
4058 copyup mvpsubcheck
4059
4060 layer psd TAP
4061 and-not PPLUS
4062 and-not NPLUS
4063 and-not POLY
4064 and-not THKOX
4065 and-not pfetexpand
4066 and psdexpand
4067
4068 layer nsd TAP
4069 and-not PPLUS
4070 and-not NPLUS
4071 and-not POLY
4072 and-not THKOX
4073 and nsdexpand
4074
4075 layer mvpsd TAP
4076 and-not PPLUS
4077 and-not NPLUS
4078 and-not POLY
4079 and THKOX
4080 and-not mvpfetexpand
4081 and mvpsdexpand
4082
4083 layer mvnsd TAP
4084 and-not PPLUS
4085 and-not NPLUS
4086 and-not POLY
4087 and THKOX
4088 and mvnsdexpand
4089
4090 templayer hresarea POLY
4091 and RPM
4092 grow 3000
4093
4094 templayer uresarea POLY
4095 and URPM
4096 grow 3000
4097
4098 templayer diffresarea DIFFRES
4099 and-not THKOX
4100 grow 3000
4101
4102 templayer mvdiffresarea DIFFRES
4103 and THKOX
4104 grow 3000
4105
4106 templayer resarea diffresarea,mvdiffresarea,hresarea,uresarea
4107
4108 layer pfet POLY
4109 and DIFF
4110 and diffresarea
4111 and-not NPLUS
4112 and-not STDCELL
4113
4114 layer scpfet POLY
4115 and DIFF
4116 and diffresarea
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]4117 and-not HVTP
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4118 and-not NPLUS
4119 and STDCELL
4120
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4121 layer scpfethvt POLY
4122 and DIFF
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4123 and diffresarea
Tim Edwardsfe5a33e2020-11-14 15:52:11 -0500[diff] [blame]4124 and HVTP
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]4125 and-not NPLUS
4126 and STDCELL
4127
4128 templayer xpolyterm RPM,URPM
4129 and POLY
4130 and-not POLYRES
4131 # add back the 0.06um contact surround in the direction of the resistor
4132 grow 60
4133 and POLY
4134
4135 layer xpc xpolyterm
4136
4137 templayer polyarea POLY
4138 and-not POLYRES
4139 and-not POLYSHORT
4140 and-not DIFF
4141 and-not RPM
4142 and-not URPM
4143 copyup polycheck
4144
4145 layer poly polyarea,POLYTXT,POLYPIN
4146 labels POLY
4147 labels POLYTXT port
4148 labels POLYPIN port
4149
4150 # Copy (non-resistor) poly areas up for contact checks
4151 templayer xpolycheck polycheck
4152 copyup polycheck
4153
4154 layer mrp1 POLY
4155 and POLYRES
4156 and-not RPM
4157 and-not URPM
4158 labels POLY
4159
4160 layer rmp POLY
4161 and POLYSHORT
4162 labels POLY
4163
4164 layer xhrpoly POLY
4165 and POLYRES
4166 and RPM
4167 and-not URPM
4168 and PPLUS
4169 and NPC
4170 and-not xpolyterm
4171 labels POLY
4172
4173 layer uhrpoly POLY
4174 and POLYRES
4175 and URPM
4176 and-not RPM
4177 and NPC
4178 and-not xpolyterm
4179 labels POLY
4180
4181 templayer ndcbase CONT
4182 and DIFF
4183 and NPLUS
4184 and-not NWELL
4185 and LI
4186 and-not THKOX
4187
4188 layer ndc ndcbase
4189 grow 85
4190 shrink 85
4191 shrink 85
4192 grow 85
4193 or ndcbase
4194 labels CONT
4195
4196 templayer nscbase CONT
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4197 and DIFF,TAP
4198 and NPLUS
4199 and NWELL
4200 and LI
4201 and-not THKOX
4202
4203 layer nsc nscbase
4204 grow 85
4205 shrink 85
4206 shrink 85
4207 grow 85
4208 or nscbase
4209 labels CONT
4210
4211 templayer pdcbase CONT
4212 and DIFF
4213 and PPLUS
4214 and NWELL
4215 and LI
4216 and-not THKOX
4217
4218 layer pdc pdcbase
4219 grow 85
4220 shrink 85
4221 shrink 85
4222 grow 85
4223 or pdcbase
4224 labels CONT
4225
4226 templayer pdcnowell CONT
4227 and DIFF
4228 and PPLUS
4229 and pfetexpand
4230 and LI
4231 and-not THKOX
4232
4233 layer pdc pdcnowell
4234 grow 85
4235 shrink 85
4236 shrink 85
4237 grow 85
4238 or pdcnowell
4239 labels CONT
4240
4241 templayer pscbase CONT
4242 and DIFF,TAP
4243 and PPLUS
4244 and-not NWELL
4245 and-not pfetexpand
4246 and LI
4247 and-not THKOX
4248
4249 layer psc pscbase
4250 grow 85
4251 shrink 85
4252 shrink 85
4253 grow 85
4254 or pscbase
4255 labels CONT
4256
4257 templayer pcbase CONT
4258 and POLY
4259 and-not DIFF
4260 and-not RPM,URPM
4261 and LI
4262
4263 layer pc pcbase
4264 grow 85
4265 shrink 85
4266 shrink 85
4267 grow 85
4268 or pcbase
4269 labels CONT
4270
4271 templayer ndicbase CONT
4272 and DIFF
4273 and NPLUS
4274 and DIODE
4275 and-not POLY
4276 and-not PPLUS
4277 and-not THKOX
4278 and-not LVTN
4279
4280 layer ndic ndicbase
4281 grow 85
4282 shrink 85
4283 shrink 85
4284 grow 85
4285 or ndicbase
4286 labels CONT
4287
4288 templayer ndilvtcbase CONT
4289 and DIFF
4290 and NPLUS
4291 and DIODE
4292 and-not POLY
4293 and-not PPLUS
4294 and-not THKOX
4295 and LVTN
4296
4297 layer ndilvtc ndilvtcbase
4298 grow 85
4299 shrink 85
4300 shrink 85
4301 grow 85
4302 or ndilvtcbase
4303 labels CONT
4304
4305 templayer pdicbase CONT
4306 and DIFF
4307 and PPLUS
4308 and DIODE
4309 and-not POLY
4310 and-not NPLUS
4311 and-not THKOX
4312 and-not LVTN
4313 and-not HVTP
4314
4315 layer pdic pdicbase
4316 grow 85
4317 shrink 85
4318 shrink 85
4319 grow 85
4320 or pdicbase
4321 labels CONT
4322
4323 templayer pdilvtcbase CONT
4324 and DIFF
4325 and PPLUS
4326 and DIODE
4327 and-not POLY
4328 and-not NPLUS
4329 and-not THKOX
4330 and LVTN
4331 and-not HVTP
4332
4333 layer pdilvtc pdilvtcbase
4334 grow 85
4335 shrink 85
4336 shrink 85
4337 grow 85
4338 or pdilvtcbase
4339 labels CONT
4340
4341 templayer pdihvtcbase CONT
4342 and DIFF
4343 and PPLUS
4344 and DIODE
4345 and-not POLY
4346 and-not NPLUS
4347 and-not THKOX
4348 and-not LVTN
4349 and HVTP
4350
4351 layer pdihvtc pdihvtcbase
4352 grow 85
4353 shrink 85
4354 shrink 85
4355 grow 85
4356 or pdihvtcbase
4357 labels CONT
4358
4359 templayer mvndcbase CONT
4360 and DIFF
4361 and NPLUS
4362 and-not NWELL
4363 and LI
4364 and THKOX
4365
4366 layer mvndc mvndcbase
4367 grow 85
4368 shrink 85
4369 shrink 85
4370 grow 85
4371 or mvndcbase
4372 labels CONT
4373
4374 templayer mvnscbase CONT
4375 and DIFF,TAP
4376 and NPLUS
4377 and NWELL
4378 and LI
4379 and THKOX
4380
4381 layer mvnsc mvnscbase
4382 grow 85
4383 shrink 85
4384 shrink 85
4385 grow 85
4386 or mvnscbase
4387 labels CONT
4388
4389 templayer mvpdcbase CONT
4390 and DIFF
4391 and PPLUS
4392 and NWELL
4393 and LI
4394 and THKOX
4395
4396 layer mvpdc mvpdcbase
4397 grow 85
4398 shrink 85
4399 shrink 85
4400 grow 85
4401 or mvpdcbase
4402 labels CONT
4403
4404 templayer mvpdcnowell CONT
4405 and DIFF
4406 and PPLUS
4407 and mvpfetexpand
4408 and MET1
4409 and THKOX
4410
4411 layer mvpdc mvpdcnowell
4412 grow 85
4413 shrink 85
4414 shrink 85
4415 grow 85
4416 or mvpdcnowell
4417 labels CONT
4418
4419 templayer mvpscbase CONT
4420 and DIFF,TAP
4421 and PPLUS
4422 and-not NWELL
4423 and-not mvpfetexpand
4424 and LI
4425 and THKOX
4426
4427 layer mvpsc mvpscbase
4428 grow 85
4429 shrink 85
4430 shrink 85
4431 grow 85
4432 or mvpscbase
4433 labels CONT
4434
4435 templayer mvndicbase CONT
4436 and DIFF
4437 and NPLUS
4438 and DIODE
4439 and-not POLY
4440 and-not PPLUS
4441 and-not LVTN
4442 and THKOX
4443
4444 layer mvndic mvndicbase
4445 grow 85
4446 shrink 85
4447 shrink 85
4448 grow 85
4449 or mvndicbase
4450 labels CONT
4451
4452 templayer nndicbase CONT
4453 and DIFF
4454 and NPLUS
4455 and DIODE
4456 and-not POLY
4457 and-not PPLUS
4458 and LVTN
4459 and THKOX
4460
4461 layer nndic nndicbase
4462 grow 85
4463 shrink 85
4464 shrink 85
4465 grow 85
4466 or nndicbase
4467 labels CONT
4468
4469 templayer mvpdicbase CONT
4470 and DIFF
4471 and PPLUS
4472 and DIODE
4473 and-not POLY
4474 and-not NPLUS
4475 and THKOX
4476
4477 layer mvpdic mvpdicbase
4478 grow 85
4479 shrink 85
4480 shrink 85
4481 grow 85
4482 or mvpdicbase
4483 labels CONT
4484
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]4485 layer coreli LI,LITXT,LIPIN
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4486 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]4487 and COREID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4488 labels LI
4489 labels LITXT port
4490 labels LIPIN port
4491
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]4492 layer locali LI,LITXT,LIPIN
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4493 and-not LIRES,LISHORT
Tim Edwardsfaac36a2020-11-06 20:37:24 -0500[diff] [blame]4494 and-not COREID
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4495 labels LI
4496 labels LITXT port
4497 labels LIPIN port
4498
4499 layer rli LI
4500 and LIRES,LISHORT
4501 labels LIRES,LISHORT
4502
4503 layer lic MCON
4504 grow 95
4505 shrink 95
4506 shrink 85
4507 grow 85
4508 or MCON
4509 labels MCON
4510
4511 layer m1 MET1,MET1TXT,MET1PIN
4512 and-not MET1RES,MET1SHORT
4513 labels MET1
4514 labels MET1TXT port
4515 labels MET1PIN port
4516
4517 layer rm1 MET1
4518 and MET1RES,MET1SHORT
4519 labels MET1RES,MET1SHORT
4520
4521 layer m1fill MET1FILL
4522 labels MET1FILL
4523
4524#ifdef MIM
4525 layer mimcap MET3
4526 and CAPM
4527 labels CAPM
4528
4529 layer mimcc VIA3
4530 and CAPM
4531 grow 60
4532 grow 40
4533 shrink 40
4534 labels CAPM
4535
4536 layer mimcap2 MET4
4537 and CAPM2
4538 labels CAPM2
4539
4540 layer mim2cc VIA4
4541 and CAPM2
4542 grow 190
4543 grow 210
4544 shrink 210
4545 labels CAPM2
4546
4547#endif (MIM)
4548
4549 templayer m2cbase VIA1
4550 grow 55
4551
4552 layer m2c m2cbase
4553 grow 30
4554 shrink 30
4555 shrink 130
4556 grow 130
4557 or m2cbase
4558
4559 layer m2 MET2,MET2TXT,MET2PIN
4560 and-not MET2RES,MET2SHORT
4561 labels MET2
4562 labels MET2TXT port
4563 labels MET2PIN port
4564
4565 layer rm2 MET2
4566 and MET2RES,MET2SHORT
4567 labels MET2RES,MET2SHORT
4568
4569 layer m2fill MET2FILL
4570 labels MET2FILL
4571
4572 templayer m3cbase VIA2
4573 grow 40
4574
4575 layer m3c m3cbase
4576 grow 60
4577 shrink 60
4578 shrink 140
4579 grow 140
4580 or m3cbase
4581
4582 layer m3 MET3,MET3TXT,MET3PIN
4583 and-not MET3RES,MET3SHORT
4584#ifdef MIM
4585 and-not CAPM
4586#endif (MIM)
4587 labels MET3
4588 labels MET3TXT port
4589 labels MET3PIN port
4590
4591 layer rm3 MET3
4592 and MET3RES,MET3SHORT
4593 labels MET3RES,MET3SHORT
4594
4595 layer m3fill MET3FILL
4596 labels MET3FILL
4597
4598#ifdef (METAL5)
4599
4600 templayer via3base VIA3
4601#ifdef MIM
4602 and-not CAPM
4603#endif (MIM)
4604 grow 60
4605
4606 layer via3 via3base
4607 grow 40
4608 shrink 40
4609 shrink 160
4610 grow 160
4611 or via3base
4612
4613 layer m4 MET4,MET4TXT,MET4PIN
4614 and-not MET4RES,MET4SHORT
4615#ifdef MIM
4616 and-not CAPM2
4617#endif (MIM)
4618 labels MET4
4619 labels MET4TXT port
4620 labels MET4PIN port
4621
4622 layer rm4 MET4
4623 and MET4RES,MET4SHORT
4624 labels MET4RES,MET4SHORT
4625
4626 layer m4fill MET4FILL
4627 labels MET4FILL
4628
4629 layer m5 MET5,MET5TXT,MET5PIN
4630 and-not MET5RES,MET5SHORT
4631 labels MET5
4632 labels MET5TXT port
4633 labels MET5PIN port
4634
4635 layer rm5 MET5
4636 and MET5RES,MET5SHORT
4637 labels MET5RES,MET5SHORT
4638
4639 layer m5fill MET5FILL
4640 labels MET5FILL
4641
4642 templayer via4base VIA4
4643#ifdef MIM
4644 and-not CAPM2
4645#endif (MIM)
4646 grow 190
4647
4648 layer via4 via4base
4649 grow 210
4650 shrink 210
4651 shrink 590
4652 grow 590
4653 or via4base
4654#endif (METAL5)
4655
4656#ifdef REDISTRIBUTION
4657 layer metrdl RDL,RDLTXT,RDLPIN
4658 labels RDL
4659 labels RDLTXT port
4660 labels RDLPIN port
4661#endif
4662
4663 # Find diffusion not covered in
4664 # NPLUS or PPLUS and pull it into
4665 # the next layer up
4666
4667 templayer gentrans DIFF
4668 and-not PPLUS
4669 and-not NPLUS
4670 and POLY
4671 copyup DIFF,POLY
4672
4673 templayer gendiff DIFF,TAP
4674 and-not PPLUS
4675 and-not NPLUS
4676 and-not POLY
4677 copyup DIFF
4678
4679 # Handle contacts found by copyup
4680
4681 templayer ndiccopy CONT
4682 and LI
4683 and DIODE
4684 and NPLUS
4685 and-not THKOX
4686
4687 layer ndic ndiccopy
4688 grow 85
4689 shrink 85
4690 shrink 85
4691 grow 85
4692 or ndiccopy
4693 labels CONT
4694
4695 templayer mvndiccopy CONT
4696 and LI
4697 and DIODE
4698 and NPLUS
4699 and THKOX
4700
4701 layer mvndic mvndiccopy
4702 grow 85
4703 shrink 85
4704 shrink 85
4705 grow 85
4706 or mvndiccopy
4707 labels CONT
4708
4709 templayer pdiccopy CONT
4710 and LI
4711 and DIODE
4712 and PPLUS
4713 and-not THKOX
4714
4715 layer pdic pdiccopy
4716 grow 85
4717 shrink 85
4718 shrink 85
4719 grow 85
4720 or pdiccopy
4721 labels CONT
4722
4723 templayer mvpdiccopy CONT
4724 and LI
4725 and DIODE
4726 and PPLUS
4727 and THKOX
4728
4729 layer mvpdic mvpdiccopy
4730 grow 85
4731 shrink 85
4732 shrink 85
4733 grow 85
4734 or mvpdiccopy
4735 labels CONT
4736
4737 templayer ndccopy CONT
4738 and ndifcheck
4739
4740 layer ndc ndccopy
4741 grow 85
4742 shrink 85
4743 shrink 85
4744 grow 85
4745 or ndccopy
4746 labels CONT
4747
4748 templayer mvndccopy CONT
4749 and mvndifcheck
4750
4751 layer mvndc mvndccopy
4752 grow 85
4753 shrink 85
4754 shrink 85
4755 grow 85
4756 or mvndccopy
4757 labels CONT
4758
4759 templayer pdccopy CONT
4760 and pdifcheck
4761
4762 layer pdc pdccopy
4763 grow 85
4764 shrink 85
4765 shrink 85
4766 grow 85
4767 or pdccopy
4768 labels CONT
4769
4770 templayer mvpdccopy CONT
4771 and mvpdifcheck
4772
4773 layer mvpdc mvpdccopy
4774 grow 85
4775 shrink 85
4776 shrink 85
4777 grow 85
4778 or mvpdccopy
4779 labels CONT
4780
4781 templayer pccopy CONT
4782 and polycheck
4783
4784 layer pc pccopy
4785 grow 85
4786 shrink 85
4787 shrink 85
4788 grow 85
4789 or pccopy
4790 labels CONT
4791
4792 templayer nsccopy CONT
4793 and nsubcheck
4794
4795 layer nsc nsccopy
4796 grow 85
4797 shrink 85
4798 shrink 85
4799 grow 85
4800 or nsccopy
4801 labels CONT
4802
4803 templayer mvnsccopy CONT
4804 and mvnsubcheck
4805
4806 layer mvnsc mvnsccopy
4807 grow 85
4808 shrink 85
4809 shrink 85
4810 grow 85
4811 or mvnsccopy
4812 labels CONT
4813
4814 templayer psccopy CONT
4815 and psubcheck
4816
4817 layer psc psccopy
4818 grow 85
4819 shrink 85
4820 shrink 85
4821 grow 85
4822 or psccopy
4823 labels CONT
4824
4825 templayer mvpsccopy CONT
4826 and mvpsubcheck
4827
4828 layer mvpsc mvpsccopy
4829 grow 85
4830 shrink 85
4831 shrink 85
4832 grow 85
4833 or mvpsccopy
4834 labels CONT
4835
4836 # Find contacts not covered in
4837 # metal and pull them into the
4838 # next layer up
4839
4840 templayer gencont CONT
4841 and LI
4842 and-not DIFF,TAP
4843 and-not POLY
4844 and-not DIODE
4845 and-not nsubcheck
4846 and-not psubcheck
4847 and-not mvnsubcheck
4848 and-not mvpsubcheck
4849 copyup CONT,LI
4850
4851 templayer barecont CONT
4852 and-not LI
4853 and-not nsubcheck
4854 and-not psubcheck
4855 and-not mvnsubcheck
4856 and-not mvpsubcheck
4857 copyup CONT
4858
4859 layer glass GLASS,PADTXT,PADPIN
4860 labels GLASS
4861 labels PADTXT port
4862 labels PADPIN port
4863
4864 templayer boundary BOUND,STDCELL,PADCELL
4865 boundary
4866
4867 layer comment LVSTEXT
4868 labels LVSTEXT text
4869
4870 layer comment TTEXT
4871 labels TTEXT text
4872
4873 layer fillblock FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
4874 labels FILLOBSM1,FILLOBSM2,FILLOBSM3,FILLOBSM4
4875
4876# MOS Varactor
4877
4878 layer var POLY
4879 and TAP
4880 and NPLUS
4881 and NWELL
4882 and-not THKOX
4883 and-not HVTP
4884 # NOTE: Else forms a varactor that is not in the vendor netlist.
4885 and-not COREID
4886 labels POLY
4887
4888 layer varhvt POLY
4889 and TAP
4890 and NPLUS
4891 and NWELL
4892 and-not THKOX
4893 and HVTP
4894 labels POLY
4895
4896 layer mvvar POLY
4897 and TAP
4898 and NPLUS
4899 and NWELL
4900 and THKOX
4901 labels POLY
4902
4903 calma NWELL 64 20
4904 calma DIFF 65 20
4905 calma DNWELL 64 18
4906 calma PWRES 64 13
4907 calma TAP 65 44
4908 # LVTN
4909 calma LVTN 125 44
4910 # HVTR
4911 calma HVTR 18 20
4912 # HVTP
4913 calma HVTP 78 44
4914 # SONOS (TUNM)
4915 calma SONOS 80 20
4916 # NPLUS = NSDM
4917 calma NPLUS 93 44
4918 # PPLUS = PSDM
4919 calma PPLUS 94 20
4920 # HVI
4921 calma THKOX 75 20
4922 # NPC
4923 calma NPC 95 20
4924 # P+ POLY MASK
4925 calma RPM 86 20
4926 calma URPM 79 20
4927 calma LDNTM 11 44
4928 calma HVNTM 125 20
Tim Edwards3360b9e2020-09-16 11:45:19 -0400[diff] [blame]4929 # Poly resistor ID mark
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4930 calma POLYRES 66 13
4931 # Diffusion resistor ID mark
4932 calma DIFFRES 65 13
4933 calma POLY 66 20
4934 calma POLYMOD 66 83
4935 # Diode ID mark
4936 calma DIODE 81 23
4937 # Bipolar NPN mark
4938 calma NPNID 82 20
4939 # Bipolar PNP mark
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]4940 calma PNPID 82 44
Tim Edwards88baa8e2020-08-30 17:03:58 -0400[diff] [blame]4941 # Capacitor ID
4942 calma CAPID 82 64
4943 # Core area ID mark
4944 calma COREID 81 2
4945 # Standard cell ID mark
4946 calma STDCELL 81 4
4947 # Padframe cell ID mark
4948 calma PADCELL 81 3
4949 # Seal ring ID mark
4950 calma SEALID 81 1
4951 # Low tap density ID mark
4952 calma LOWTAPDENSITY 81 14
4953
4954 # LICON
4955 calma CONT 66 44
4956 calma LI 67 20
4957 calma MCON 67 44
4958
4959 calma MET1 68 20
4960 calma VIA1 68 44
4961 calma MET2 69 20
4962 calma VIA2 69 44
4963 calma MET3 70 20
4964#ifdef METAL5
4965 calma VIA3 70 44
4966 calma MET4 71 20
4967 calma VIA4 71 44
4968 calma MET5 72 20
4969#endif
4970#ifdef REDISTRIBUTION
4971 calma RDL 74 20
4972#endif
4973 calma GLASS 76 20
4974
4975 calma SUBPIN 64 59
4976 calma PADPIN 76 5
4977 calma DIFFPIN 65 6
4978 calma TAPPIN 65 5
4979 calma WELLPIN 64 5
4980 calma LIPIN 67 5
4981 calma POLYPIN 66 5
4982 calma MET1PIN 68 5
4983 calma MET2PIN 69 5
4984 calma MET3PIN 70 5
4985#ifdef METAL5
4986 calma MET4PIN 71 5
4987 calma MET5PIN 72 5
4988#endif
4989#ifdef REDISTRIBUTION
4990 calma RDLPIN 74 5
4991#endif
4992
4993 calma LIRES 67 13
4994 calma MET1RES 68 13
4995 calma MET2RES 69 13
4996 calma MET3RES 70 13
4997#ifdef METAL5
4998 calma MET4RES 71 13
4999 calma MET5RES 72 13
5000#endif
5001
5002 calma MET1FILL 68 28
5003 calma MET2FILL 69 28
5004 calma MET3FILL 70 28
5005#ifdef METAL5
5006 calma MET4FILL 71 28
5007 calma MET5FILL 72 28
5008#endif
5009
5010 calma POLYSHORT 66 15
5011 calma LISHORT 67 15
5012 calma MET1SHORT 68 15
5013 calma MET2SHORT 69 15
5014 calma MET3SHORT 70 15
5015#ifdef METAL5
5016 calma MET4SHORT 71 15
5017 calma MET5SHORT 72 15
5018#endif
5019
5020 calma SUBTXT 122 16
5021 calma PADTXT 76 16
5022 calma DIFFTXT 65 16
5023 calma POLYTXT 66 16
5024 calma WELLTXT 64 16
5025 calma LITXT 67 16
5026 calma MET1TXT 68 16
5027 calma MET2TXT 69 16
5028 calma MET3TXT 70 16
5029#ifdef METAL5
5030 calma MET4TXT 71 16
5031 calma MET5TXT 72 16
5032#endif
5033#ifdef REDISTRIBUTION
5034 calma RDLPIN 74 16
5035#endif
5036
5037 calma BOUND 235 4
5038
5039 calma LVSTEXT 83 44
5040
5041#ifdef (MIM)
5042 calma CAPM 89 44
5043 calma CAPM2 97 44
5044#endif (MIM)
5045
5046 calma FILLOBSM1 62 24
5047 calma FILLOBSM2 105 52
5048 calma FILLOBSM3 107 24
5049 calma FILLOBSM4 112 4
5050
5051end
5052
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5053#-----------------------------------------------------
5054# Digital flow maze router cost parameters
5055#-----------------------------------------------------
5056
5057mzrouter
5058end
5059
5060#-----------------------------------------------------
5061# Vendor DRC rules
5062#-----------------------------------------------------
5063
5064drc
5065
5066 style drc variants (fast),(full),(routing)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5067 scalefactor 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5068 cifstyle drc
5069
5070 variants (fast),(full)
5071
5072#-----------------------------
5073# DNWELL
5074#-----------------------------
5075
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5076 width dnwell 3000 "Deep N-well width < %d (dnwell.2)"
5077 spacing dnwell dnwell 6300 touching_ok "Deep N-well spacing < %d (dnwell.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5078 spacing dnwell allnwell 4500 surround_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5079 "Deep N-well spacing to N-well < %d (nwell.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5080
5081 variants (full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5082 cifmaxwidth nwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5083 "N-well overlap of Deep N-well < 0.4um outside, 1.03um inside (nwell.5a, 7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5084 cifmaxwidth dnwell_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5085 "SONOS nFET must be in Deep N-well (tunm.6a)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5086
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5087 cifmaxwidth pdiff_crosses_dnwell 0 bend_illegal \
5088 "P+ diff cannot straddle Deep N-well (dnwell.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5089 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5090
5091#-----------------------------
5092# NWELL
5093#-----------------------------
5094
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5095 width allnwell 840 "N-well width < %d (nwell.1)"
5096 spacing allnwell allnwell 1270 touching_ok "N-well spacing < %d (nwell.2a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5097
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5098 variants (full)
5099 cifmaxwidth nwell_missing_tap 0 bend_illegal \
5100 "All nwells must contain metal-connected N+ taps (nwell.4)"
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]5101
5102 cifspacing mvnwell lvnwell 2000 touching_illegal \
5103 "Spacing of HV nwell to LV nwell < 2.0um (nwell.8)"
5104 cifspacing mvnwell mvnwell 2000 touching_ok \
5105 "Spacing of HV nwell to HV nwell < 2.0um (nwell.8)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5106 variants (fast),(full)
5107
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5108#-----------------------------
5109# DIFF
5110#-----------------------------
5111
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5112 width *ndiff,nfet,scnfet,npd,npass,*nsd,*ndiode,ndiffres,*pdiff,pfet,scpfet,scpfethvt,ppu,*psd,*pdiode,pdiffres \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5113 150 "Diffusion width < %d (diff/tap.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5114 width *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,*mvpdiff,mvpfet,*mvpdiode 290 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5115 "MV Diffusion width < %d (diff/tap.14)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5116
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5117 width *mvnsd,*mvpsd 150 "MV Tap width < %d (diff/tap.1)"
5118 extend *mvpsd *mvndiff 700 "MV Butting tap length < %d (diff/tap.16)"
5119 extend *mvnsd *mvpdiff 700 "MV Butting tap length < %d (diff/tap.16)"
5120 extend *psd *ndiff 290 "Butting tap length < %d (diff/tap.4)"
5121 extend *nsd *pdiff 290 "Butting tap length < %d (diff/tap.4)"
5122 width mvpdiffres 150 "MV P-Diffusion resistor width < %d (diff/tap.14a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5123 spacing alldifflv,var,varhvt alldifflv,var,varhvt 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5124 "Diffusion spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5125 spacing alldiffmvnontap,mvvar alldiffmvnontap,mvvar 300 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5126 "MV Diffusion spacing < %d (diff/tap.15a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5127 spacing alldiffmv *mvnsd,*mvpsd 270 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5128 "MV Diffusion to MV tap spacing < %d (diff/tap.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5129 spacing *mvndiff,mvnfet,mvnnfet,*mvndiode,*nndiode,mvndiffres,mvvar *mvpsd 370 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5130 touching_ok "MV P-Diffusion to MV N-tap spacing < %d (diff/tap.15b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5131 spacing *mvnsd,*mvpdiff,mvpfet,mvvar,*mvpdiode *mvpsd,*psd 760 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5132 "MV Diffusion in N-well to P-tap spacing < %d (diff/tap.20 + diff/tap.17,19)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5133 spacing *ndiff,*ndiode,nfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5134 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5135 spacing *mvndiff,*mvndiode,mvnfet,mvnnfet allnwell 340 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5136 "N-Diffusion spacing to N-well < %d (diff/tap.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5137 spacing *psd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5138 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5139 spacing *mvpsd allnwell 130 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5140 "P-tap spacing to N-well < %d (diff/tap.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5141 surround *nsd allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5142 "N-well overlap of N-tap < %d (diff/tap.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5143 surround *mvnsd allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5144 "N-well overlap of MV N-tap < %d (diff/tap.19)"
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5145 surround *pdiff,*pdiode,pfet,scpfet,ppu allnwell 180 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5146 "N-well overlap of P-Diffusion < %d (diff/tap.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5147 surround *mvpdiff,*mvpdiode,mvpfet allnwell 330 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5148 "N-well overlap of P-Diffusion < %d (diff/tap.17)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5149 surround mvvar allnwell 560 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5150 "N-well overlap of MV varactor < %d (lvtn.10 + lvtn.4b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5151 spacing *mvndiode *mvndiode 1070 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5152 "MV N-diode spacing < %d (hvntm.2 + 2 * hvntm.3)"
Tim Edwards2bdf3b92020-11-13 10:48:53 -0500[diff] [blame]5153
5154variants (full)
5155 cifspacing allmvdiffnowell lvnwell 825 touching_illegal \
5156 "MV diffusion to LV nwell spacing < %d (hvi.5 + nsd/psd.5)"
5157variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5158
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5159 spacing allnfets allpactivenonfet 270 touching_illegal \
5160 "nFET cannot abut P-diffusion (diff/tap.3)"
5161 spacing allpfets allnactivenonfet 270 touching_illegal \
5162 "pFET cannot abut N-diffusion (diff/tap.3)"
5163
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5164 # Butting junction rules
5165 edge4way (*psd)/a ~(*ndiff,*psd)/a 125 ~(*ndiff)/a (*ndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5166 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5167 edge4way (*ndiff)/a ~(*ndiff,*psd)/a 125 ~(*psd)/a (*psd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5168 "N-Diffusion to P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5169 edge4way (*nsd)/a ~(*pdiff,*nsd)/a 125 ~(*pdiff)/a (*pdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5170 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5171 edge4way (*pdiff)/a ~(*pdiff,*nsd)/a 125 ~(*nsd)/a (*nsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5172 "P-Diffusion to N-tap spacing < %d across butted junction (nsd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5173
5174 edge4way (*mvpsd)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvndiff)/a (*mvndiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5175 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5176 edge4way (*mvndiff)/a ~(*mvndiff,*mvpsd)/a 125 ~(*mvpsd)/a (*mvpsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5177 "MV N-Diffusion to MV P-tap spacing < %d across butted junction (psd.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5178 edge4way (*mvnsd)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvpdiff)/a (*mvpdiff)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5179 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5180 edge4way (*mvpdiff)/a ~(*mvpdiff,*mvnsd)/a 125 ~(*mvnsd)/a (*mvnsd)/a 125 \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5181 "MV P-Diffusion to MV N-tap spacing < %d across butted junction (nsd.5a)"
5182
5183 # Sandwiched butting junction restrictions
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5184 edge4way (*pdiff)/a (*nsd)/a 400 ~(*pdiff)/a 0 0 "NSDM width < %d (diff/tap.5)"
5185 edge4way (*ndiff)/a (*psd)/a 400 ~(*ndiff)/a 0 0 "PSDM width < %d (diff/tap.5)"
5186
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]5187 area *nsd,*mvnsd 70110 150 "N-tap minimum area < 0.07011um^2 (nsd.10b)"
5188 area *psd,*mvpsd 70110 150 "P-tap minimum area < 0.07011um^2 (psd.10b)"
5189
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5190 angles allactive 90 "Only 90 degree angles permitted on diff and tap (x.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5191
5192 variants (full)
Tim Edwardsa91a1172020-11-12 21:10:13 -0500[diff] [blame]5193 cifmaxwidth tap_missing_licon 0 bend_illegal "All taps must be contacted (licon.16)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5194
5195 # Latchup rules
5196 cifmaxwidth ptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5197 "N-diff distance to P-tap must be < 15.0um (LU.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5198 cifmaxwidth dptap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5199 "N-diff distance to P-tap in deep nwell.must be < 15.0um (LU.2.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5200 cifmaxwidth ntap_missing 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5201 "P-diff distance to N-tap must be < 15.0um (LU.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5202
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5203 variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5204
5205#-----------------------------
5206# POLY
5207#-----------------------------
5208
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5209 width allpoly 150 "poly width < %d (poly.1a)"
5210 spacing allpoly allpoly 210 touching_ok "poly spacing < %d (poly.2)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5211
5212 spacing allpolynonfet \
Tim Edwardse363ce42020-11-12 19:18:33 -0500[diff] [blame]5213 *ndiff,*mvndiff,*ndiode,*nndiode,ndiffres,*ndiodelvt,*pdiff,*mvpdiff,*pdiode,pdiffres,*pdiodelvt,*pdiodehvt \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5214 75 corner_ok allfets \
5215 "poly spacing to Diffusion < %d (poly.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5216 spacing npres *nsd 480 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5217 "poly resistor spacing to N-tap < %d (poly.9)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5218 overhang *ndiff,rndiff nfet,scnfet,npd,npass 250 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5219 overhang *mvndiff,mvrndiff mvnfet,mvnnfet 250 \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5220 "N-Diffusion overhang of nFET < %d (poly.7)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5221 overhang *pdiff,rpdiff pfet,scpfet,ppu 250 "P-Diffusion overhang of pmos < %d (poly.7)"
5222 overhang *mvpdiff,mvrpdiff mvpfet 250 "P-Diffusion overhang of pmos < %d (poly.7)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5223 overhang *poly allfets 130 "poly overhang of transistor < %d (poly.8)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5224 rect_only allfets "No bends in transistors (poly.11)"
5225 rect_only xhrpoly,uhrpoly "No bends in poly resistors (poly.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5226 extend xpc/a xhrpoly,uhrpoly 2160 \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5227 "poly contact extends poly resistor by < %d (licon.1c + li.5)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5228 spacing xhrpoly,uhrpoly,xpc xhrpoly,uhrpoly,xpc 1240 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5229 "Distance between precision resistors < %d (rpm.2 + 2 * rpm.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5230
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5231 spacing xhrpoly,uhrpoly,xpc allndifflv,allndiffmv 780 touching_illegal \
5232 "Distance from precision resistor to N+ diffusion < %d (rpm.3 + rpm.6 + nsd.5a)"
5233 spacing xhrpoly,uhrpoly,xpc *poly 400 touching_illegal \
5234 "Distance from precision resistor to unrelated poly < %d (rpm.3 + rpm.7)"
5235 spacing xhrpoly,uhrpoly,xpc allndiffmvnontap 830 touching_illegal \
5236 "Distance from precision resistor to MV N+ diffusion < %d (rpm.3 + rpm.9)"
5237
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5238 angles allpoly 90 "Only 90 degree angles permitted on poly (x.2)"
5239
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5240#--------------------------------------------------------------------
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5241# HVTP
5242#--------------------------------------------------------------------
5243
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5244 spacing pfethvt,pdiodehvt,varactorhvt pfet,ppu,scpfet,mvpfet,pfetlvt,pfetmvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5245 360 touching_illegal \
5246 "Min. spacing between pFET and HVTP < %d (hvtp.4)"
5247
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5248 spacing pfethvt,pdiodehvt,varactorhvt varactor 360 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5249 "Min. spacing between varactor and HVTP < %d (hvtp.4 + varac.3)"
5250
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5251#--------------------------------------------------------------------
5252# LVTN
5253#--------------------------------------------------------------------
5254
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5255 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt \
5256 allfetsnolvt 360 touching_illegal \
5257 "Min. spacing between FET and LVTN < %d (lvtn.3a)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5258
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5259 spacing pfetlvt,nfetlvt,pdiodelvt,ndiodelvt scpfethvt,pfethvt,pdiodehvt,varactorhvt \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5260 740 touching_illegal \
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5261 "Min. spacing between LVTN and HVTP < %d (lvtn.9)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5262
5263 # Spacing across S/D direction requires edge rule
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5264 edge4way allfetsnolvt allactivenonfet 415 \
5265 ~(pfetlvt,nfetlvt,pdiodelvt,ndiodelvt)/a allfetsnolvt 415 \
5266 "Min. spacing between FET and LVTN in S/D direction < %d (lvtn.3b)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5267
5268#--------------------------------------------------------------------
5269# NPC (Nitride poly Cut)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5270#--------------------------------------------------------------------
5271
5272# Layer NPC is defined automatically around poly contacts (grow 0.1um)
5273
5274#--------------------------------------------------------------------
5275# CONT (LICON, contact between poly/diff and LI)
5276#--------------------------------------------------------------------
5277
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5278 width ndc/li 170 "N-diffusion contact width < %d (licon.1)"
5279 width nsc/li 170 "N-tap contact width < %d (licon.1)"
5280 width pdc/li 170 "P-diffusion contact width < %d (licon.1)"
5281 width psc/li 170 "P-tap contact width < %d (licon.1)"
5282 width ndic/li 170 "N-diode contact width < %d (licon.1)"
5283 width pdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5284 width pc/li 170 "poly contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5285
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5286 width xpc/li 350 "poly resistor contact width < %d (licon.1b + 2 * li.5)"
5287 area xpc/li 700000 350 "poly resistor contact length < 2.0um (licon.1c)"
5288 area allli,*obsli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5289
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5290 width mvndc/li 170 "N-diffusion contact width < %d (licon.1)"
5291 width mvnsc/li 170 "N-tap contact width < %d (licon.1)"
5292 width mvpdc/li 170 "P-diffusion contact width < %d (licon.1)"
5293 width mvpsc/li 170 "P-tap contact width < %d (licon.1)"
5294 width mvndic/li 170 "N-diode contact width < %d (licon.1)"
5295 width mvpdic/li 170 "P-diode contact width < %d (licon.1)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5296
5297 spacing allpdiffcont allndiffcont 170 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5298 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5299 spacing allndiffcont allndiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5300 "Diffusion contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5301 spacing allpdiffcont allpdiffcont 170 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5302 "Diffusion contact spacing < %d (licon.2)"
5303 spacing pc pc 170 touching_ok "Poly1 contact spacing < %d (licon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5304
5305 spacing pc alldiff 190 touching_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5306 "poly contact spacing to diffusion < %d (licon.14)"
5307 spacing pc allpdifflv,allpdiffmv 235 touching_illegal \
5308 "poly contact spacing to P-diffusion < %d (licon.9 + psdm.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5309
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5310 spacing ndc,pdc nfet,nfetlvt,pfet,pfethvt,pfetlvt,pfetmvt 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5311 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5312 spacing ndc,pdc scnfet,npd,npass,scpfet,scpfethvt,ppu 50 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5313 "Diffusion contact to standard cell gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5314 spacing mvndc,mvpdc mvnfet,mvnnfet,mvpfet 55 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5315 "Diffusion contact to gate < %d (licon.11)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5316 spacing nsc varactor,varhvt 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5317 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5318 spacing mvnsc mvvar 250 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5319 "Diffusion contact to varactor gate < %d (licon.10)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5320
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5321 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5322 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5323 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5324 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5325 surround ndic/a *ndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5326 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5327 surround pdic/a *pdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5328 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5329
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5330 spacing psc/a allnactivenontap 60 touching_illegal \
5331 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
5332 spacing nsc/a allpactivenontap 60 touching_illegal \
5333 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
5334
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5335 surround ndc/a *ndiff,nfet,scnfet,npd,npass,nfetlvt 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5336 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5337 surround pdc/a *pdiff,pfet,scpfet,scpfethvt,ppu,pfethvt,pfetmvt,pfetlvt 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5338 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5339 surround ndic/a *ndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5340 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5341 surround pdic/a *pdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5342 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5343
5344 surround nsc/a *nsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5345 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5346 surround psc/a *psd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5347 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5348
5349 surround mvndc/a *mvndiff,mvnfet 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5350 "N-diffusion overlap of N-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5351 surround mvpdc/a *mvpdiff,mvpfet 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5352 "P-diffusion overlap of P-diffusion contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5353 surround mvndic/a *mvndi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5354 "N-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5355 surround mvpdic/a *mvpdi 40 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5356 "P-diode overlap of N-diode contact < %d (licon.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5357
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5358 spacing mvpsc/a allndiffmvnontap 60 touching_illegal \
5359 "Min. space between P-tap contact and butting N diffusion < %d (licon.5b)"
5360 spacing mvnsc/a allpdiffmvnontap 60 touching_illegal \
5361 "Min. space between N-tap contact and butting P diffusion < %d (licon.5b)"
5362
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5363 surround mvndc/a *mvndiff,mvnfet 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5364 "N-diffusion overlap of N-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5365 surround mvpdc/a *mvpdiff,mvpfet 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5366 "P-diffusion overlap of P-diffusion contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5367 surround mvndic/a *mvndi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5368 "N-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5369 surround mvpdic/a *mvpdi 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5370 "P-diode overlap of N-diode contact < %d in one direction (licon.5c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5371
5372 surround mvnsc/a *mvnsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5373 "N-tap overlap of N-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5374 surround mvpsc/a *mvpsd 120 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5375 "P-tap overlap of P-tap contact < %d in one direction (licon.7)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5376
5377 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 50 absence_illegal \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5378 "poly overlap of poly contact < %d (licon.8)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5379 surround pc/a *poly,mrp1,xhrpoly,uhrpoly 80 directional \
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5380 "poly overlap of poly contact < %d in one direction (licon.8a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5381
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5382 exact_overlap (allcont)/a
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5383
5384#-------------------------------------------------------------
5385# LI - Local interconnect layer
5386#-------------------------------------------------------------
5387
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5388variants *
5389
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5390 width *li 170 "Local interconnect width < %d (li.1)"
5391 width rli 290 "Local interconnect width < %d (li.7)"
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]5392
5393 # Note: coreli width rule uses edge4way rule so as not to imply that
5394 # all li contact types can also be minimum width 0.14um.
5395 edge4way ~(coreli,pc,ndc,nsc,pdc,psc)/li coreli 140 coreli,pc,ndc,nsc,pdc,psc \
5396 0 0 "Core local interconnect width < %d (li.c1)"
5397
5398 # width coreli 140 "Core local interconnect width < %d (li.c1)"
5399
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5400 spacing allli allli,*obsli 170 touching_ok "Local interconnect spacing < %d (li.3)"
5401 spacing coreli allli,*obsli 140 touching_ok "Core local interconnect spacing < %d (li.c2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5402
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]5403 surround pc/li *li,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5404 "Local interconnect overlap of poly contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5405
5406 surround ndc/li,nsc/li,pdc/li,psc/li,ndic/li,pdic/li,mvndc/li,mvnsc/li,mvpdc/li,mvpsc/li,mvndic/li,mvpdic/li \
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]5407 *li,rli,coreli 80 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5408 "Local interconnect overlap of diffusion contact < %d in one direction (li.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5409
Tim Edwards22ff74f2020-11-23 20:31:11 -0500[diff] [blame]5410 area allli,*obsli,coreli 56100 170 "Local interconnect minimum area < %a (li.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5411
Tim Edwardsb04723d2020-11-13 19:48:27 -0500[diff] [blame]5412 angles *locali,rli 90 "Only 90 degree angles permitted on local interconnect (x.2)"
5413 angles coreli 45 \
5414 "Only 45 degree angles permitted on local interconnect in SRAM cell (x.2)"
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5415
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5416#-------------------------------------------------------------
5417# MCON - Contact between local interconnect and metal1
5418#-------------------------------------------------------------
5419
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5420 width lic/m1 170 "mcon.width < %d (mcon.1)"
Tim Edwards5b50e7a2020-10-17 17:31:49 -0400[diff] [blame]5421 spacing lic/m1 lic/m1,obslic/m1 190 touching_ok "mcon.spacing < %d (mcon.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5422
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5423 exact_overlap lic/li
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5424
5425#-------------------------------------------------------------
5426# METAL1 -
5427#-------------------------------------------------------------
5428
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5429 width *m1,rm1 140 "Metal1 width < %d (met1.1)"
5430 spacing allm1 allm1,*obsm1 140 touching_ok "Metal1 spacing < %d (met1.2)"
5431 area allm1,*obsm1 83000 140 "Metal1 minimum area < %a (met1.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5432
5433 surround lic/m1 *met1 30 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5434 "Metal1 overlap of local interconnect contact < %d (met1.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5435 surround lic/m1 *met1 60 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5436 "Metal1 overlap of local interconnect contact < %d in one direction (met1.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5437
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5438 angles allm1 45 "Only 45 and 90 degree angles permitted on metal1 (x.3a)"
5439
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5440variants (fast),(full)
5441 widespacing allm1 3000 allm1,*obsm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5442 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5443 widespacing *obsm1 3000 allm1 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5444 "Metal1 > 3um spacing to unrelated m1 < %d (met1.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5445
5446variants (full)
5447 cifmaxwidth m1_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5448 "Min area of metal1 holes > 0.14um^2 (met1.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5449
5450 cifspacing m1_large_halo m1_large_halo 280 touching_ok \
5451 "Spacing of metal1 features attached to and within 0.28um of large metal1 < %d (met1.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5452variants *
5453
5454#--------------------------------------------------
5455# VIA1
5456#--------------------------------------------------
5457
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5458 width v1/m1 260 "Via1 width < %d (via.1a + 2 * via.4a)"
5459 spacing v1 v1 60 touching_ok "Via1 spacing < %d (via.2 - 2 * via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5460 surround v1/m1 *m1 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5461 "Metal1 overlap of Via1 < %d in one direction (via.5a - via.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5462 surround v1/m2 *m2 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5463 "Metal2 overlap of Via1 < %d in one direction (met2.5 - met2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5464
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5465 exact_overlap v1/m1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5466
5467#--------------------------------------------------
5468# METAL2 -
5469#--------------------------------------------------
5470
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5471 width allm2 140 "Metal2 width < %d (met2.1)"
5472 spacing allm2 allm2,obsm2 140 touching_ok "Metal2 spacing < %d (met2.2)"
5473 area allm2,obsm2 67600 140 "Metal2 minimum area < %a (met2.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5474
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5475 angles allm2 45 "Only 45 and 90 degree angles permitted on metal2 (x.3a)"
5476
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5477variants (fast),(full)
5478 widespacing allm2 3000 allm2,obsm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5479 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5480 widespacing obsm2 3000 allm2 280 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5481 "Metal2 > 3um spacing to unrelated m2 < %d (met2.3b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5482
5483variants (full)
5484 cifmaxwidth m2_hole_empty 0 bend_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5485 "Min area of metal2 holes > 0.14um^2 (met2.7)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5486
5487 cifspacing m2_large_halo m2_large_halo 280 touching_ok \
5488 "Spacing of metal2 features attached to and within 0.28um of large metal2 < %d (met2.3a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5489variants *
5490
5491#--------------------------------------------------
5492# VIA2
5493#--------------------------------------------------
5494
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5495 width v2/m2 280 "via2.width < %d (via2.1a + 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5496
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5497 spacing v2 v2 120 touching_ok "via2.spacing < 0.24um (via2.2 - 2 * via2.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5498
5499 surround v2/m2 *m2 45 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5500 "Metal2 overlap of via2.< %d in one direction (via2.4a - via2.4)"
5501 surround v2/m3 *m3 25 absence_illegal "Metal3 overlap of via2.< %d (met3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5502
5503 exact_overlap v2/m2
5504
5505#--------------------------------------------------
5506# METAL3 -
5507#--------------------------------------------------
5508
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5509 width allm3 300 "Metal3 width < %d (met3.1)"
5510 spacing allm3 allm3,obsm3 300 touching_ok "Metal3 spacing < %d (met3.2)"
5511 area allm3,obsm3 240000 300 "Metal3 minimum area < %a (met3.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5512
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5513 angles allm3 45 "Only 45 and 90 degree angles permitted on metal3 (x.3a)"
5514
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5515variants (fast),(full)
5516 widespacing allm3 3000 allm3,obsm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5517 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5518 widespacing obsm3 3000 allm3 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5519 "Metal3 > 3um spacing to unrelated m3 < %d (met3.3d)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]5520variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5521 cifspacing m3_large_halo m3_large_halo 400 touching_ok \
5522 "Spacing of metal3 features attached to and within 0.40um of large metal3 < %d (met3.3c)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5523variants *
5524
5525
5526#ifdef METAL5
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]5527#undef METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5528#--------------------------------------------------
5529# VIA3 - Requires METAL5 Module
5530#--------------------------------------------------
5531
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5532 width v3/m3 320 "via3.width < %d (via3.1 + 2 * via3.4)"
5533 spacing v3 v3 80 touching_ok "via3.spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5534 surround v3/m3 *m3 30 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5535 "Metal3 overlap of via3.in one direction < %d (via3.5 - via3.4)"
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]5536 surround v3/m4 *m4 5 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5537 "Metal4 overlap of via3.< %d (met4.3 - via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5538
5539 exact_overlap v3/m3
5540
5541#-----------------------------
5542# METAL4 - METAL4 Module
5543#-----------------------------
5544
5545variants *
5546
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5547 width allm4 300 "Metal4 width < %d (met4.1)"
5548 spacing allm4 allm4,obsm4 300 touching_ok "Metal4 spacing < %d (met4.2)"
5549 area allm4,obsm4 240000 300 "Metal4 minimum area < %a (met4.4a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5550
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5551 angles allm4 45 "Only 45 and 90 degree angles permitted on metal4 (x.3a)"
5552
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5553variants (fast),(full)
5554 widespacing allm4 3000 allm4,obsm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5555 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5556 widespacing obsm4 3000 allm4 400 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5557 "Metal4 > 3um spacing to unrelated m4 < %d (met4.5b)"
Tim Edwardse15b3522020-11-12 22:28:17 -0500[diff] [blame]5558variants (full)
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5559 cifspacing m4_large_halo m4_large_halo 400 touching_ok \
5560 "Spacing of metal4 features attached to and within 0.40um of large metal4 < %d (met4.5a)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5561variants *
5562
5563#--------------------------------------------------
5564# VIA4 - Requires METAL5 Module
5565#--------------------------------------------------
5566
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5567 width v4/m4 1180 "via4.width < %d (via4.1 + 2 * via4.4)"
5568 spacing v4 v4 420 touching_ok "via4.spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5569 surround v4/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5570 "Metal5 overlap of via4.< %d (met5.3 - via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5571
5572 exact_overlap v4/m4
5573
5574#-----------------------------
5575# METAL5 - METAL5 Module
5576#-----------------------------
5577
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5578 width allm5 1600 "Metal5 width < %d (met5.1)"
5579 spacing allm5 allm5,obsm5 1600 touching_ok "Metal5 spacing < %d (met5.2)"
5580 area allm5,obsm5 4000000 1600 "Metal5 minimum area < %a (met5.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5581
Tim Edwards281a8822020-11-04 13:34:27 -0500[diff] [blame]5582 angles allm5 45 "Only 45 and 90 degree angles permitted on metal5 (x.3a)"
5583
Tim Edwardseba70cf2020-08-01 21:08:46 -0400[diff] [blame]5584#define METAL5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5585#endif (METAL5)
5586
5587#ifdef REDISTRIBUTION
5588
5589variants (full)
5590
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5591 width metrdl 10000 "RDL width < %d (rdl.1)"
5592 spacing metrdl metrdl 10000 touching_ok "RDL spacing < %d (rdl.2)"
5593 surround glass metrdl 10750 absence_ok "RDL must surround glass cut by %d (rdl.3)"
5594 spacing metrdl padl 19660 surround_ok "RDL spacing to unrelated pad < %d (rdl.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5595
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5596variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5597
5598#endif (REDISTRIBUTION)
5599
5600#--------------------------------------------------
5601# NMOS, PMOS
5602#--------------------------------------------------
5603
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5604 edge4way *poly allfetsstd 420 allfets 0 0 \
5605 "Transistor width < %d (diff/tap.2)"
5606 edge4way *poly allfetsspecial 360 allfets 0 0 \
5607 "Transistor in standard cell width < %d (diff/tap.2)"
5608
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5609 # Except: Note that standard cells allow transistor width minimum 0.36um
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5610 width pfetlvt 350 "LVT PMOS gate length < %d (poly.1b)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5611
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5612 spacing allpolynonfet *nsd 55 corner_ok varactor \
5613 "poly spacing to diffusion tap < %d (poly.5)"
5614 spacing allpolynonfet *mvnsd 55 corner_ok mvvaractor \
5615 "poly spacing to diffusion tap < %d (poly.5)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5616
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]5617 edge4way *psd *ndiff 300 ~(nfet,npass,npd,scnfet,nfetlvt,nsonos)/a *psd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5618 "Butting P-tap spacing to NMOS gate < %d (poly.6)"
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5619 edge4way *nsd *pdiff 300 ~(pfet,ppu,scpfet,scpfethvt,pfetlvt,pfetmvt)/a *nsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5620 "Butting N-tap spacing to PMOS gate < %d (poly.6)"
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]5621 edge4way *mvpsd *mvndiff 300 ~(mvnfet,mvnnfet)/a *mvpsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5622 "Butting MV P-tap spacing to MV NMOS gate < %d (poly.6)"
Tim Edwards859ff4b2020-10-18 14:59:38 -0400[diff] [blame]5623 edge4way *mvnsd *mvpdiff 300 ~mvpfet/a *mvnsd 300 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5624 "Butting MV N-tap spacing to MV PMOS gate < %d (poly.6)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5625
5626 # No LV FETs in HV diff
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]5627 spacing pfet,scpfet,scpfethvt,ppu,pfetlvt,pfetmvt,pfethvt,*pdiff *mvpdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5628 "LV P-diffusion to MV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5629
Tim Edwards5ebe4cf2020-07-31 15:56:02 -0400[diff] [blame]5630 spacing nfet,scnfet,npd,npass,nfetlvt,varactor,varhvt,*ndiff *mvndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5631 "LV N-diffusion to MV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5632
5633 # No HV FETs in LV diff
5634 spacing mvpfet,*mvpdiff *pdiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5635 "MV P-diffusion to LV P-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5636
5637 spacing mvnfet,mvvaractor,*mvndiff *ndiff 360 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5638 "MV N-diffusion to LV N-diffusion < %d (diff/tap.23 + diff/tap.22)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5639
5640 # Minimum length of MV FETs. Note that this is larger than the minimum
5641 # width (0.29um), so an edge rule is required
5642
5643 edge4way mvndiff mvnfet 500 mvnfet 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5644 "MV NMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5645
5646 edge4way mvnsd mvvaractor 500 mvvaractor 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5647 "MV Varactor minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5648
5649 edge4way mvpdiff mvpfet 500 mvpfet 0 0 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5650 "MV PMOS minimum length < %d (poly.13)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5651
5652#--------------------------------------------------
5653# mrp1 (N+ poly resistor)
5654#--------------------------------------------------
5655
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5656 width mrp1 330 "mrp1 resistor width < %d (poly.3)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5657
5658#--------------------------------------------------
5659# xhrpoly (P+ poly resistor)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5660# uhrpoly (P+ poly resistor, 2kOhm/sq)
5661#--------------------------------------------------
5662
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5663 # NOTE: u/xhrpoly resistor requires discrete widths 0.35, 0.69, ... up to 1.27.
5664 width xhrpoly 350 "xhrpoly resistor width < %d (P+ poly.1a)"
5665 width uhrpoly 350 "uhrpoly resistor width < %d (P+ poly.1a)"
5666
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5667 spacing xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5668 "xhrpoly/uhrpoly resistor spacing to diffusion < %d (poly.9)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5669
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]5670 spacing mrp1,xhrpoly,uhrpoly,xpc allfets 480 touching_illegal \
Tim Edwardse162c052020-11-11 11:01:06 -0500[diff] [blame]5671 "Poly resistor spacing to poly < %d (poly.9)"
5672
5673 spacing xhrpoly,uhrpoly,xpc *poly 480 touching_illegal \
5674 "Poly resistor spacing to poly < %d (poly.9)"
5675
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]5676 spacing mrp1 *poly 480 touching_ok \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5677 "Poly resistor spacing to poly < %d (poly.9)"
5678
Tim Edwards3f7ee642020-11-25 10:26:39 -0500[diff] [blame]5679 spacing mrp1,xhrpoly,uhrpoly,xpc alldiff 480 touching_illegal \
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5680 "Poly resistor spacing to diffusion < %d (poly.9)"
5681
5682#------------------------------------
5683# nsonos
5684#------------------------------------
5685
5686variants (full)
5687 cifmaxwidth bbox_missing 0 bend_illegal \
5688 "SONOS transistor must be in cell with abutment box (tunm.8)"
5689variants (fast),(full)
5690
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5691#------------------------------------
5692# MOS Varactor device rules
5693#------------------------------------
5694
5695 overhang *nsd var,varhvt 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5696 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5697
5698 overhang *mvnsd mvvar 250 \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5699 "N-Tap overhang of Varactor < %d (var.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5700
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5701 width var,varhvt,mvvar 180 "Varactor length < %d (var.1)"
5702 extend var,varhvt,mvvar *poly 1000 "Varactor width < %d (var.2)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5703
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5704variants (full)
5705 cifmaxwidth var_poly_no_nwell 0 bend_illegal \
5706 "N-well overlap of varactor poly < 0.15um (varac.5)"
5707
5708 cifmaxwidth pdiff_in_varactor_well 0 bend_illegal \
5709 "Varactor N-well must not contain P+ diffusion (varac.7)"
5710variants (fast),(full)
5711
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5712#ifdef MIM
5713#-----------------------------------------------------------
5714# MiM CAP (CAPM) -
5715#-----------------------------------------------------------
5716
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]5717 width *mimcap 1000 "MiM cap width < %d (capm.1)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5718 spacing *mimcap *mimcap 840 touching_ok "MiM cap spacing < %d (capm.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]5719 spacing *mimcap via3/m3 80 touching_illegal \
5720 "MiM cap spacing to via3 < %d (capm.5 - via3.4)"
5721 surround *mimcc *mimcap 80 absence_illegal \
5722 "MiM cap must surround MiM cap contact by %d (capm.4 - via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5723 rect_only *mimcap "MiM cap must be rectangular (capm.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5724
5725 surround *mimcap *metal3/m3 140 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5726 "Metal3 must surround MiM cap by %d (capm.3)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]5727 spacing via2 *mimcap 100 touching_illegal \
5728 "MiM cap spacing to via2 < %d (capm.8 - via2.4)"
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]5729 spacing *mimcap *metal3/m3 500 surround_ok \
5730 "MiM cap spacing to unrelated metal3 < %d (capm.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5731
5732variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]5733 cifspacing mim_bottom mim_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]5734 "MiM cap bottom plate spacing < %d (capm.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5735variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5736
5737 # MiM cap contact rules (VIA3)
5738
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5739 width mimcc/c1 320 "MiM cap contact width < %d (via3.1 + 2 * via3.4)"
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5740 spacing mimcc mimcc 80 touching_ok "MiM cap contact spacing < %d (via3.2 - 2 * via3.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5741 surround mimcc/m4 *m4 5 directional \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5742 "Metal4 overlap of MiM cap contact in one direction < %d (met4.3 - via3.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5743 exact_overlap mimcc/c1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5744
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]5745 width *mimcap2 1000 "MiM2 cap width < %d (cap2m.1)"
5746 spacing *mimcap2 *mimcap2 840 touching_ok "MiM2 cap spacing < %d (cap2m.2a)"
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]5747 spacing *mimcap2 via4/m4 10 touching_illegal \
5748 "MiM2 cap spacing to via4 < %d (cap2m.5 - via4.4)"
5749 surround *mim2cc *mimcap2 10 absence_illegal \
5750 "MiM2 cap must surround MiM cap 2 contact by %d (cap2m.4 - via4.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]5751 rect_only *mimcap2 "MiM2 cap must be rectangular (cap2m.7)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5752
5753 surround *mimcap2 *metal4/m4 140 absence_illegal \
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]5754 "Metal4 must surround MiM2 cap by %d (cap2m.3)"
Tim Edwards5ad4eb42020-11-27 10:58:22 -0500[diff] [blame]5755 spacing via3,mimcc *mimcap2 80 touching_illegal \
Tim Edwards9314dea2020-11-27 10:48:02 -0500[diff] [blame]5756 "MiM2 cap spacing to via3 < %d (cap2m.8 - via3.4)"
Tim Edwards32712912020-11-07 16:18:39 -0500[diff] [blame]5757 spacing *mimcap2 *metal4/m4 500 surround_ok \
5758 "MiM2 cap spacing to unrelated metal4 < %d (cap2m.11)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5759
5760variants (full)
Tim Edwards95effb32020-10-17 14:56:41 -0400[diff] [blame]5761 cifspacing mim2_bottom mim2_bottom 1200 touching_ok \
Tim Edwards2788f172020-10-14 22:32:33 -0400[diff] [blame]5762 "MiM2 cap bottom plate spacing < %d (cap2m.2b)"
Tim Edwardse6a454b2020-10-17 22:52:39 -0400[diff] [blame]5763variants (fast),(full)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5764
5765 # MiM cap contact rules (VIA4)
5766
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5767 width mim2cc/c2 1180 "MiM2 cap contact width < %d (via4.1 + 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5768 spacing mim2cc mim2cc 420 touching_ok \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5769 "MiM2 cap contact spacing < %d (via4.2 - 2 * via4.4)"
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5770 surround mim2cc/m5 *m5 120 absence_illegal \
Tim Edwards96c1e832020-09-16 11:42:16 -0400[diff] [blame]5771 "Metal5 overlap of MiM2 cap contact < %d (met5.3 - via4.4)"
Tim Edwardsc879cf02020-09-20 22:09:50 -0400[diff] [blame]5772 exact_overlap mim2cc/c2
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5773
5774#endif (MIM)
5775
5776#----------------------------
Tim Edwards0984f472020-11-12 21:37:36 -0500[diff] [blame]5777# HVNTM
5778#----------------------------
5779variants (full)
5780 cifspacing hvntm_generate hvntm_generate 700 touching_ok \
5781 "HVNTM spacing < %d (hvntm.2)"
5782variants (fast),(full)
5783
5784#----------------------------
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5785# End DRC style
5786#----------------------------
5787
5788end
5789
5790#----------------------------
5791# LEF format definitions
5792#----------------------------
5793
5794lef
5795
Tim Edwards282d9542020-07-15 17:52:08 -0400[diff] [blame]5796 masterslice pwell pwell PWELL substrate
5797 masterslice nwell nwell NWELL
Tim Edwardsd9fe0002020-07-14 21:53:24 -0400[diff] [blame]5798
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5799 routing li li1 LI1 LI li
5800
5801 routing m1 met1 MET1 m1
5802 routing m2 met2 MET2 m2
5803 routing m3 met3 MET3 m3
5804#ifdef METAL5
5805 routing m4 met4 MET4 m4
5806 routing m5 met5 MET5 m5
5807#endif (METAL5)
5808#ifdef REDISTRIBUTION
5809 routing mrdl met6 MET6 m6 MRDL METRDL
5810#endif
5811
5812 cut lic mcon MCON Mcon
5813 cut m2c via via1 VIA VIA1 cont2 via12
5814 cut m3c via2 VIA2 cont3 via23
5815#ifdef METAL5
5816 cut via3 via3 VIA3 cont4 via34
5817 cut via4 via4 VIA4 cont5 via45
5818#endif (METAL5)
5819
5820 obs obsli li1
5821 obs obsm1 met1
5822 obs obsm2 met2
5823 obs obsm3 met3
5824
5825#ifdef METAL5
5826 obs obsm4 met4
5827 obs obsm5 met5
5828#endif (METAL5)
5829#ifdef REDISTRIBUTION
5830 obs obsmrdl met6
5831#endif
5832
Tim Edwards42f79a32020-09-21 14:18:09 -0400[diff] [blame]5833 # NOTE: obslic only used with li1, not obsli.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5834 obs obslic mcon
5835
5836end
5837
5838#-----------------------------------------------------
5839# Device and Parasitic extraction
5840#-----------------------------------------------------
5841
5842
5843extract
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5844 style ngspice variants (),(orig),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5845 cscale 1
5846 # NOTE: SkyWater SPICE libraries use .option scale 1E6 so all
5847 # dimensions must be in units of microns in the extract file.
5848 # Use extract style "ngspice(si)" to override this and produce
5849 # a file with SI units for length/area.
5850
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]5851 variants (),(orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]5852 lambda 1E6
5853 variants (si)
5854 lambda 1.0
5855 variants *
5856
5857 units microns
5858 step 7
5859 sidehalo 2
5860
5861 # NOTE: MiM cap layers have been purposely put out of order,
5862 # may want to reconsider.
5863
5864 planeorder dwell 0
5865 planeorder well 1
5866 planeorder active 2
5867 planeorder locali 3
5868 planeorder metal1 4
5869 planeorder metal2 5
5870 planeorder metal3 6
5871#ifdef METAL5
5872 planeorder metal4 7
5873 planeorder metal5 8
5874#ifdef REDISTRIBUTION
5875 planeorder metali 9
5876 planeorder block 10
5877 planeorder comment 11
5878 planeorder cap1 12
5879 planeorder cap2 13
5880#else (!REDISTRIBUTION)
5881 planeorder block 9
5882 planeorder comment 10
5883 planeorder cap1 11
5884 planeorder cap2 12
5885#endif (!REDISTRIBUTION)
5886#else (!METAL5)
5887#ifdef REDISTRIBUTION
5888 planeorder metali 7
5889 planeorder block 8
5890 planeorder comment 9
5891 planeorder cap1 10
5892 planeorder cap2 11
5893#else (!REDISTRIBUTION)
5894 planeorder block 7
5895 planeorder comment 8
5896 planeorder cap1 9
5897 planeorder cap2 10
5898#endif (!REDISTRIBUTION)
5899#endif (!METAL5)
5900
5901 height dnwell -0.1 0.1
5902 height nwell,pwell 0.0 0.2062
5903 height alldiff 0.2062 0.12
5904 height allpoly 0.3262 0.18
5905 height alldiffcont 0.3262 0.61
5906 height pc 0.5062 0.43
5907 height allli 0.9361 0.10
5908 height lic 1.0361 0.34
5909 height allm1 1.3761 0.36
5910 height v1 1.7361 0.27
5911 height allm2 2.0061 0.36
5912 height v2 2.3661 0.42
5913 height allm3 2.7861 0.845
5914#ifdef METAL5
5915 height v3 3.6311 0.39
5916 height allm4 4.0211 0.845
5917 height v4 4.8661 0.505
5918 height allm5 5.3711 1.26
5919 height mimcap 2.4661 0.2
5920 height mimcap2 3.7311 0.2
5921 height mimcc 2.6661 0.12
5922 height mim2cc 3.9311 0.09
5923#ifdef REDISTRIBUTION
5924 height mrdlc 6.6311 5.2523
5925 height mrdl 11.8834 4.0
5926#endif (!REDISTRIBUTION)
5927#endif (!METAL5)
5928
5929 # Antenna check parameters
5930 # Note that checks w/diode diffusion are not modeled
5931 model partial
5932 antenna poly sidewall 50 none
5933 antenna allcont surface 3 none
5934 antenna li sidewall 75 0 450
5935 antenna lic surface 3 0 18
5936 antenna m1,m2,m3 sidewall 400 2600 400
5937 antenna v1 surface 3 0 18
5938 antenna v2 surface 6 0 36
5939#ifdef METAL5
5940 antenna m4,m5 sidewall 400 2600 400
5941 antenna v3,v4 surface 6 0 36
5942#endif (METAL5)
5943
5944 tiedown alldiffnonfet
5945
5946 substrate *ppdiff,*mvppdiff,space/w,pwell well $SUB -dnwell
5947
5948# Layer resistance: Use document xp018-PDS-v4_2_1.pdf
5949
5950# Resistances are in milliohms per square
5951# Optional 3rd argument is the corner adjustment fraction
5952# Device values come from trtc.cor (typical corner)
5953 resist (dnwell)/dwell 2200000
5954 resist (pwell)/well 3050000
5955 resist (nwell)/well 1700000
5956 resist (rpw)/well 3050000 0.5
5957 resist (*ndiff,nsd)/active 120000
5958 resist (*pdiff,*psd)/active 197000
5959 resist (*mvndiff,mvnsd)/active 114000
5960 resist (*mvpdiff,*mvpsd)/active 191000
5961
5962 resist ndiffres/active 120000 0.5
5963 resist pdiffres/active 197000 0.5
5964 resist mvndiffres/active 114000 0.5
5965 resist mvpdiffres/active 191000 0.5
5966 resist mrp1/active 48200 0.5
5967 resist xhrpoly/active 319800 0.5
5968 resist uhrpoly/active 2000000 0.5
5969
5970 resist (allpolynonres)/active 48200
5971 resist rmp/active 48200
5972
5973 resist (allli)/locali 12200
5974 resist (allm1)/metal1 125
5975 resist (allm2)/metal2 125
5976 resist (allm3)/metal3 47
5977#ifdef METAL5
5978 resist (allm4)/metal4 47
5979 resist (allm5)/metal5 29
5980#endif (METAL5)
5981#ifdef REDISTRIBUTION
5982 resist mrdl/metali 5
5983#endif (REDISTRIBUTION)
5984
5985 contact ndc,nsc 15000
5986 contact pdc,psc 15000
5987 contact mvndc,mvnsc 15000
5988 contact mvpdc,mvpsc 15000
5989 contact pc 15000
5990 contact lic 152000
5991 contact m2c 4500
5992 contact m3c 3410
5993#ifdef METAL5
5994#ifdef MIM
5995 contact mimcc 4500
5996 contact mim2cc 3410
5997#endif (MIM)
5998 contact via3 3410
5999 contact via4 380
6000#endif (METAL5)
6001#ifdef REDISTRIBUTION
6002 contact mrdlc 6
6003#endif (REDISTRIBUTION)
6004
6005#-------------------------------------------------------------------------
6006# Parasitic capacitance values: Use document (...)
6007#-------------------------------------------------------------------------
6008# This uses the new "default" definitions that determine the intervening
6009# planes from the planeorder stack, take care of the reflexive sideoverlap
6010# definitions, and generally clean up the section and make it more readable.
6011#
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6012# Also uses "units microns" statement. All values are taken from the
6013# document PEX/xRC/cap_models. Fringe capacitance values are approximated.
6014# Units are aF/um^2 for area caps and aF/um for perimeter and sidewall caps.
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6015#-------------------------------------------------------------------------
6016# Remember that device capacitances to substrate are taken care of by the
6017# models. Thus, active and poly definitions ignore all "fet" types.
6018# fet types are excluded when computing parasitic capacitance to
6019# active from layers above them because poly is a shield; fet types are
6020# included for parasitics from layers above to poly. Resistor types
6021# should be removed from all parasitic capacitance calculations, or else
6022# they just create floating caps. Technically, the capacitance probably
6023# should be split between the two terminals. Unsure of the correct model.
6024#-------------------------------------------------------------------------
6025
6026#n-well
6027# NOTE: This value not found in PEX files
6028defaultareacap nwell well 120
6029
6030#n-active
6031# Rely on device models to capture *ndiff area cap
6032# Do not extract parasitics from resistors
6033# defaultareacap allnactivenonfet active 790
6034# defaultperimeter allnactivenonfet active 280
6035
6036#p-active
6037# Rely on device models to capture *pdiff area cap
6038# Do not extract parasitics from resistors
6039# defaultareacap allpactivenonfet active 810
6040# defaultperimeter allpactivenonfet active 300
6041
6042#poly
6043# Do not extract parasitics from resistors
6044# defaultsidewall allpolynonfet active 22
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6045# defaultareacap allpolynonfet active 106
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6046# defaultperimeter allpolynonfet active 57
6047
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]6048 defaultsidewall *poly active 23
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6049 defaultareacap *poly active nwell,obswell,pwell well 106
6050 defaultperimeter *poly active nwell,obswell,pwell well 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6051
6052#locali
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]6053 defaultsidewall allli locali 33
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6054 defaultareacap allli locali nwell,obswell,pwell well 37
6055 defaultperimeter allli locali nwell,obswell,pwell well 55
6056 defaultoverlap allli locali nwell well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6057
6058#locali->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6059 defaultoverlap allli locali allactivenonfet active 37
6060 defaultsideoverlap allli locali allactivenonfet active 55
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6061
6062#locali->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6063 defaultoverlap allli locali allpolynonres active 94
6064 defaultsideoverlap allli locali allpolynonres active 52
6065 defaultsideoverlap *poly active allli locali 25
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6066
6067#metal1
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]6068 defaultsidewall allm1 metal1 45
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6069 defaultareacap allm1 metal1 nwell,obswell,pwell well 26
6070 defaultperimeter allm1 metal1 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6071 defaultoverlap allm1 metal1 nwell well 26
6072
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6073#metal1->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6074 defaultoverlap allm1 metal1 allactivenonfet active 26
6075 defaultsideoverlap allm1 metal1 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6076
6077#metal1->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6078 defaultoverlap allm1 metal1 allpolynonres active 45
6079 defaultsideoverlap allm1 metal1 allpolynonres active 47
6080 defaultsideoverlap *poly active allm1 metal1 17
6081
6082#metal1->locali
6083 defaultoverlap allm1 metal1 allli locali 114
6084 defaultsideoverlap allm1 metal1 allli locali 59
6085 defaultsideoverlap allli locali allm1 metal1 35
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6086
6087#metal2
Tim Edwards411f5d12020-07-11 14:58:57 -0400[diff] [blame]6088 defaultsidewall allm2 metal2 50
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6089 defaultareacap allm2 metal2 nwell,obswell,pwell well 17
6090 defaultperimeter allm2 metal2 nwell,obswell,pwell well 41
6091 defaultoverlap allm2 metal2 nwell well 38
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6092
6093#metal2->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6094 defaultoverlap allm2 metal2 allactivenonfet active 17
6095 defaultsideoverlap allm2 metal2 allactivenonfet active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6096
6097#metal2->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6098 defaultoverlap allm2 metal2 allpolynonres active 24
6099 defaultsideoverlap allm2 metal2 allpolynonres active 41
6100 defaultsideoverlap *poly active allm2 metal2 11
6101
6102#metal2->locali
6103 defaultoverlap allm2 metal2 allli locali 38
6104 defaultsideoverlap allm2 metal2 allli locali 46
6105 defaultsideoverlap allli locali allm2 metal2 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6106
6107#metal2->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6108 defaultoverlap allm2 metal2 allm1 metal1 134
6109 defaultsideoverlap allm2 metal2 allm1 metal1 67
6110 defaultsideoverlap allm1 metal1 allm2 metal2 48
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6111
6112#metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6113 defaultsidewall allm3 metal3 63
6114 defaultoverlap allm3 metal3 nwell well 12
6115 defaultareacap allm3 metal3 nwell,obswell,pwell well 12
6116 defaultperimeter allm3 metal3 nwell,obswell,pwell well 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6117
6118#metal3->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6119 defaultoverlap allm3 metal3 allactive active 12
6120 defaultsideoverlap allm3 metal3 allactive active 41
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6121
6122#metal3->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6123 defaultoverlap allm3 metal3 allpolynonres active 16
6124 defaultsideoverlap allm3 metal3 allpolynonres active 44
6125 defaultsideoverlap *poly active allm3 metal3 9
6126
6127#metal3->locali
6128 defaultoverlap allm3 metal3 allli locali 21
6129 defaultsideoverlap allm3 metal3 allli locali 47
6130 defaultsideoverlap allli locali allm3 metal3 15
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6131
6132#metal3->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6133 defaultoverlap allm3 metal3 allm1 metal1 35
6134 defaultsideoverlap allm3 metal3 allm1 metal1 55
6135 defaultsideoverlap allm1 metal1 allm3 metal3 27
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6136
6137#metal3->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6138 defaultoverlap allm3 metal3 allm2 metal2 86
6139 defaultsideoverlap allm3 metal3 allm2 metal2 70
6140 defaultsideoverlap allm2 metal2 allm3 metal3 44
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6141
6142#ifdef METAL5
6143#metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6144 defaultsidewall allm4 metal4 67
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6145# defaultareacap alltopm metal4 well 6
6146 areacap allm4/m4 8
6147 defaultoverlap allm4 metal4 nwell well 8
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6148 defaultperimeter allm4 metal4 well 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6149
6150#metal4->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6151 defaultoverlap allm4 metal4 allactivenonfet active 8
6152 defaultsideoverlap allm4 metal4 allactivenonfet active 37
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6153
6154#metal4->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6155 defaultoverlap allm4 metal4 allpolynonres active 10
6156 defaultsideoverlap allm4 metal4 allpolynonres active 38
6157 defaultsideoverlap *poly active allm4 metal4 6
6158
6159#metal4->locali
6160 defaultoverlap allm4 metal4 allli locali 12
6161 defaultsideoverlap allm4 metal4 allli locali 40
6162 defaultsideoverlap allli locali allm4 metal4 10
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6163
6164#metal4->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6165 defaultoverlap allm4 metal4 allm1 metal1 15
6166 defaultsideoverlap allm4 metal4 allm1 metal1 43
6167 defaultsideoverlap allm1 metal1 allm4 metal4 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6168
6169#metal4->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6170 defaultoverlap allm4 metal4 allm2 metal2 20
6171 defaultsideoverlap allm4 metal4 allm2 metal2 46
6172 defaultsideoverlap allm2 metal2 allm4 metal4 22
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6173
6174#metal4->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6175 defaultoverlap allm4 metal4 allm3 metal3 84
6176 defaultsideoverlap allm4 metal4 allm3 metal3 71
6177 defaultsideoverlap allm3 metal3 allm4 metal4 43
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6178
6179#metal5
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6180 defaultsidewall allm5 metal5 127
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6181# defaultareacap allm5 metal5 well 6
6182 areacap allm5/m5 6
6183 defaultoverlap allm5 metal5 nwell well 6
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6184 defaultperimeter allm5 metal5 well 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6185
6186#metal5->diff
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6187 defaultoverlap allm5 metal5 allactivenonfet active 6
6188 defaultsideoverlap allm5 metal5 allactivenonfet active 39
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6189
6190#metal5->poly
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6191 defaultoverlap allm5 metal5 allpolynonres active 7
6192 defaultsideoverlap allm5 metal5 allpolynonres active 40
6193 defaultsideoverlap *poly active allm5 metal5 6
6194
6195#metal5->locali
6196 defaultoverlap allm5 metal5 allli locali 8
6197 defaultsideoverlap allm5 metal5 allli locali 41
6198 defaultsideoverlap allli locali allm5 metal5 8
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6199
6200#metal5->metal1
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6201 defaultoverlap allm5 metal5 allm1 metal1 9
6202 defaultsideoverlap allm5 metal5 allm1 metal1 43
6203 defaultsideoverlap allm1 metal1 allm5 metal5 12
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6204
6205#metal5->metal2
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6206 defaultoverlap allm5 metal5 allm2 metal2 11
6207 defaultsideoverlap allm5 metal5 allm2 metal2 46
6208 defaultsideoverlap allm2 metal2 allm5 metal5 16
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6209
6210#metal5->metal3
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6211 defaultoverlap allm5 metal5 allm3 metal3 20
6212 defaultsideoverlap allm5 metal5 allm3 metal3 54
6213 defaultsideoverlap allm3 metal3 allm5 metal5 28
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6214
6215#metal5->metal4
Tim Edwardsa043e432020-07-10 16:50:44 -0400[diff] [blame]6216 defaultoverlap allm5 metal5 allm4 metal4 68
6217 defaultsideoverlap allm5 metal5 allm4 metal4 83
6218 defaultsideoverlap allm4 metal4 allm5 metal5 47
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6219#endif (METAL5)
6220
Tim Edwards0a0272b2020-07-28 14:40:10 -0400[diff] [blame]6221#ifdef REDISTRIBUTION
6222#endif (REDISTRIBUTION)
6223
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6224# Devices: Base models (not subcircuit wrappers)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6225
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6226variants (),(si)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6227
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6228 device msubcircuit sky130_fd_pr__pfet_01v8 pfet,scpfet \
6229 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6230 device msubcircuit sky130_fd_pr__special_pfet_pass ppu \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6231 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
6232 device msubcircuit sky130_fd_pr__pfet_01v8_lvt pfetlvt \
6233 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
6234 device msubcircuit sky130_fd_pr__pfet_01v8_mvt pfetmvt \
6235 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6236 device msubcircuit sky130_fd_pr__pfet_01v8_hvt pfethvt,scpfethvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6237 *pdiff,pdiffres *pdiff,pdiffres nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6238
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6239 device msubcircuit sky130_fd_pr__nfet_01v8 nfet,scnfet \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6240 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6241 device msubcircuit sky130_fd_pr__special_nfet_latch npd \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6242 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6243 device msubcircuit sky130_fd_pr__special_nfet_pass npass \
6244 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6245 device msubcircuit sky130_fd_pr__nfet_01v8_lvt nfetlvt \
6246 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6247 device msubcircuit sky130_fd_bs_flash__special_sonosfet_star nsonos \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6248 *ndiff,ndiffres *ndiff,ndiffres pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6249 device subcircuit sky130_fd_pr__cap_var_lvt varactor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6250 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6251 device subcircuit sky130_fd_pr__cap_var_hvt varhvt \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6252 *nndiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6253 device subcircuit sky130_fd_pr__cap_var mvvaractor \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6254 *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6255
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]6256 # Bipolars
6257 device msubcircuit sky130_fd_pr__npn_05v0 npn dnwell *ndiff space/w error a2=area
6258 device msubcircuit sky130_fd_pr__pnp_05v0 pnp pwell,space/w *pdiff a2=area
6259 device msubcircuit sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
6260
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]6261 # Ignore the extended-drain FET geometry that forms part of the high-voltage
6262 # bipolar devices.
Tim Edwardsc40fe0f2020-10-26 13:11:45 -0400[diff] [blame]6263 device msubcircuit Ignore mvnfet *mvndiff,mvndiffres dnwell pwell,space/w error +npn,pnp
6264 device msubcircuit Ignore mvpfet *mvpdiff,mvpdiffres pwell,space/w nwell error +npn,pnp
Tim Edwardsaea401b2020-10-26 13:07:32 -0400[diff] [blame]6265
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6266 # Extended drain devices (must appear before the regular devices)
6267 device msubcircuit sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
6268 dnwell pwell,space/w error l=l w=w
6269 device msubcircuit sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
6270 dnwell pwell,space/w error l=l w=w
6271 device msubcircuit sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
6272 pwell,space/w nwell error l=l w=w
6273
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6274 device msubcircuit sky130_fd_pr__pfet_g5v0d10v5 mvpfet \
6275 *mvpdiff,mvpdiffres *mvpdiff,mvpdiffres nwell error l=l w=w
6276 device msubcircuit sky130_fd_pr__nfet_g5v0d10v5 mvnfet \
6277 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
6278 device msubcircuit sky130_fd_pr__nfet_05v0_nvt mvnnfet \
6279 *mvndiff,mvndiffres *mvndiff,mvndiffres pwell,space/w error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6280
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6281 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
6282 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
6283 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
6284 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6285#ifdef METAL5
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6286 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
6287 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6288#endif (METAL5)
6289
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6290 device rsubcircuit sky130_fd_pr__res_high_po_0p35 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6291 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6292 device rsubcircuit sky130_fd_pr__res_high_po_0p69 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6293 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6294 device rsubcircuit sky130_fd_pr__res_high_po_1p41 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6295 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6296 device rsubcircuit sky130_fd_pr__res_high_po_2p85 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6297 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6298 device rsubcircuit sky130_fd_pr__res_high_po_5p73 xhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6299 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6300 device rsubcircuit sky130_fd_pr__res_high_po xhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6301 xpc pwell,space/w error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6302 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p35 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6303 xpc pwell,space/w error +res0p35 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6304 device rsubcircuit sky130_fd_pr__res_xhigh_po_0p69 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6305 xpc pwell,space/w error +res0p69 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6306 device rsubcircuit sky130_fd_pr__res_xhigh_po_1p41 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6307 xpc pwell,space/w error +res1p41 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6308 device rsubcircuit sky130_fd_pr__res_xhigh_po_2p85 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6309 xpc pwell,space/w error +res2p85 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6310 device rsubcircuit sky130_fd_pr__res_xhigh_po_5p73 uhrpoly \
Tim Edwardsd53c8002020-11-22 15:07:06 -0500[diff] [blame]6311 xpc pwell,space/w error +res5p73 l=l
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6312 device rsubcircuit sky130_fd_pr__res_xhigh_po uhrpoly \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6313 xpc pwell,space/w error l=l w=w
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6314
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]6315 device rsubcircuit sky130_fd_pr__res_generic_nd ndiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6316 *ndiff pwell,space/w error l=l w=w
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]6317 device rsubcircuit sky130_fd_pr__res_generic_pd pdiffres \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6318 *pdiff nwell error l=l w=w
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6319 device rsubcircuit sky130_fd_pr__res_iso_pw rpw \
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6320 pwell dnwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6321
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6322 device resistor sky130_fd_pr__res_generic_po rmp *poly
6323 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
6324 device resistor sky130_fd_pr__res_generic_nd__hv mvndiffres *mvndiff
6325 device resistor sky130_fd_pr__res_generic_pd__hv mvpdiffres *mvpdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6326
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6327 device subcircuit sky130_fd_pr__diode_pd2nw_05v5 *pdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6328 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6329 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt \
6330 nwell a=area
Tim Edwards2f132fd2020-11-19 09:14:30 -0500[diff] [blame]6331 device subcircuit sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt \
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6332 nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6333 device subcircuit sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6334 nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6335
6336 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5 *ndiode \
6337 pwell,space/w a=area
6338 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt \
6339 pwell,space/w a=area
6340 device msubcircuit sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode \
6341 pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6342 device msubcircuit sky130_fd_pr__diode_pw2nd_11v0 *mvndiode \
Tim Edwards862eeac2020-09-09 12:20:07 -0400[diff] [blame]6343 pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6344
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6345
6346#ifdef MIM
Tim Edwardsb1a18422020-10-02 08:51:29 -0400[diff] [blame]6347 device csubcircuit sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 w=w l=l
6348 device csubcircuit sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 w=w l=l
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6349#endif (MIM)
6350
Tim Edwards78cc9eb2020-08-14 16:49:57 -0400[diff] [blame]6351 variants (orig)
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6352
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6353 device mosfet sky130_fd_pr__pfet_01v8 scpfet,pfet pdiff,pdiffres,pdc nwell
6354 device mosfet sky130_fd_pr__special_pfet_pass ppu pdiff,pdiffres,pdc nwell
6355 device mosfet sky130_fd_pr__pfet_01v8_lvt pfetlvt pdiff,pdiffres,pdc nwell
6356 device mosfet sky130_fd_pr__pfet_01v8_mvt pfetmvt pdiff,pdiffres,pdc nwell
Tim Edwards363c7e02020-11-03 14:26:29 -0500[diff] [blame]6357 device mosfet sky130_fd_pr__pfet_01v8_hvt scpfethvt,pfethvt pdiff,pdiffres,pdc nwell
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6358 device mosfet sky130_fd_pr__nfet_01v8 scnfet,nfet ndiff,ndiffres,ndc pwell,space/w
6359 device mosfet sky130_fd_pr__special_nfet_pass npass ndiff,ndiffres,ndc pwell,space/w
6360 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
6361 device mosfet sky130_fd_pr__special_nfet_latch npd ndiff,ndiffres,ndc pwell,space/w
6362 device mosfet sky130_fd_pr__nfet_01v8_lvt nfetlvt ndiff,ndiffres,ndc pwell,space/w
6363 device mosfet sky130_fd_bs_flash__special_sonosfet_star nsonos ndiff,ndiffres,ndc \
6364 pwell,space/w
6365
6366 # Extended drain devices (must appear before the regular devices)
6367 device mosfet sky130_fd_pr__nfet_20v0_nvt mvnnfet *mvndiff,mvndiffres \
6368 dnwell pwell,space/w error
6369 device mosfet sky130_fd_pr__nfet_20v0 mvnfet *mvndiff,mvndiffres \
6370 dnwell pwell,space/w error
6371 device mosfet sky130_fd_pr__pfet_20v0 mvpfet *mvpdiff,mvpdiffres \
6372 pwell,space/w nwell error
6373
6374 device mosfet sky130_fd_pr__pfet_g5v0d10v5 mvpfet mvpdiff,mvpdiffres,mvpdc nwell
6375 device mosfet sky130_fd_pr__nfet_g5v0d10v5 mvnfet mvndiff,mvndiffres,mvndc pwell,space/w
6376 device mosfet sky130_fd_pr__nfet_05v0_nvt mvnnfet *mvndiff,mvndiffres pwell,space/w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6377
6378 # These devices always extract as subcircuits
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6379 device subcircuit sky130_fd_pr__cap_var_lvt varactor *nndiff nwell error l=l w=w
6380 device subcircuit sky130_fd_pr__cap_var_hvt varhvt *nndiff nwell error l=l w=w
6381 device subcircuit sky130_fd_pr__cap_var mvvaractor *mvnndiff nwell error l=l w=w
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6382
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6383 device resistor sky130_fd_pr__res_generic_po rmp *poly
6384 device resistor sky130_fd_pr__res_generic_l1 rli1 *li,coreli
6385 device resistor sky130_fd_pr__res_generic_m1 rmetal1 *metal1
6386 device resistor sky130_fd_pr__res_generic_m2 rmetal2 *metal2
6387 device resistor sky130_fd_pr__res_generic_m3 rmetal3 *metal3
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6388#ifdef METAL5
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6389 device resistor sky130_fd_pr__res_generic_m4 rm4 *m4
6390 device resistor sky130_fd_pr__res_generic_m5 rm5 *m5
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6391#endif (METAL5)
6392
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6393 device resistor sky130_fd_pr__res_high_po_0p35 xhrpoly xpc +res0p35
6394 device resistor sky130_fd_pr__res_high_po_0p69 xhrpoly xpc +res0p69
6395 device resistor sky130_fd_pr__res_high_po_1p41 xhrpoly xpc +res1p41
6396 device resistor sky130_fd_pr__res_high_po_2p85 xhrpoly xpc +res2p85
6397 device resistor sky130_fd_pr__res_high_po_5p73 xhrpoly xpc +res5p73
6398 device resistor sky130_fd_pr__res_high_po xhrpoly xpc
6399 device resistor sky130_fd_pr__res_xhigh_po_0p35 uhrpoly xpc +res0p35
6400 device resistor sky130_fd_pr__res_xhigh_po_0p69 uhrpoly xpc +res0p69
6401 device resistor sky130_fd_pr__res_xhigh_po_1p41 uhrpoly xpc +res1p41
6402 device resistor sky130_fd_pr__res_xhigh_po_2p85 uhrpoly xpc +res2p85
6403 device resistor sky130_fd_pr__res_xhigh_po_5p73 uhrpoly xpc +res5p73
6404 device resistor sky130_fd_pr__res_xhigh_po uhrpoly xpc
6405 device resistor sky130_fd_pr__res_generic_po mrp1 *poly
6406 device resistor sky130_fd_pr__res_generic_nd ndiffres *ndiff
6407 device resistor sky130_fd_pr__res_generic_pd pdiffres *pdiff
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6408 device resistor mrdn_hv mvndiffres *mvndiff
6409 device resistor mrdp_hv mvpdiffres *mvpdiff
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6410 device resistor sky130_fd_pr__res_iso_pw rpw pwell
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6411
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6412 device ndiode sky130_fd_pr__diode_pw2nd_05v5 *ndiode pwell,space/w a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6413 device ndiode sky130_fd_pr__diode_pw2nd_05v5_lvt *ndiodelvt pwell,space/w a=area
6414 device ndiode sky130_fd_pr__diode_pw2nd_05v5_nvt *nndiode pwell,space/w a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6415 device ndiode sky130_fd_pr__diode_pw2nd_11v0 *mvndiode pwell,space/w a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6416
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6417 device pdiode sky130_fd_pr__diode_pd2nw_05v5 *pdiode nwell a=area
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6418 device pdiode sky130_fd_pr__diode_pd2nw_05v5_lvt *pdiodelvt nwell a=area
6419 device pdiode sky130_fd_pr__diode_pd2nw_05v5_hvt *pdiodehvt nwell a=area
Tim Edwardsbe6f1202020-10-29 10:37:46 -0400[diff] [blame]6420 device pdiode sky130_fd_pr__diode_pd2nw_11v0 *mvpdiode nwell a=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6421
Tim Edwards1021f552020-09-11 17:37:51 -0400[diff] [blame]6422 device bjt sky130_fd_pr__npn_05v5 npn dnwell *ndiff space/w error a2=area
6423 device bjt sky130_fd_pr__pnp_05v5 pnp pwell,space/w *pdiff a2=area
Tim Edwardsfcec6442020-10-26 11:09:27 -0400[diff] [blame]6424 device bjt sky130_fd_pr__npn_11v0 npn dnwell *mvndiff space/w error a2=area
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6425
6426#ifdef MIM
Tim Edwardsd7289eb2020-09-10 21:48:31 -0400[diff] [blame]6427 device capacitor sky130_fd_pr__cap_mim_m3_1 *mimcap *m3 1
6428 device capacitor sky130_fd_pr__cap_mim_m3_2 *mimcap2 *m4 1
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6429#endif (MIM)
6430
6431end
6432
6433#-----------------------------------------------------
6434# Wiring tool definitions
6435#-----------------------------------------------------
6436
6437wiring
6438 # All wiring values are in nanometers
6439 scalefactor 10
6440
6441 contact lic 170 li 0 0 m1 30 60
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6442 contact v1 260 m1 0 30 m2 0 30
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6443 contact v2 280 m2 0 45 m3 25 0
6444#ifdef METAL5
Tim Edwardsba66a982020-07-13 13:33:41 -0400[diff] [blame]6445 contact v3 320 m3 0 30 m4 5 5
Tim Edwardsbf5ec172020-08-09 14:04:00 -0400[diff] [blame]6446 contact v4 1180 m4 0 m5 120
Tim Edwards55f4d0e2020-07-05 15:41:02 -0400[diff] [blame]6447#endif (METAL5)
6448
6449 contact pc 170 poly 50 80 li 0 80
6450 contact pdc 170 pdiff 40 60 li 0 80
6451 contact ndc 170 ndiff 40 60 li 0 80
6452 contact psc 170 psd 40 60 li 0 80
6453 contact nsc 170 nsd 40 60 li 0 80
6454
6455end
6456
6457#-----------------------------------------------------
6458# Plain old router. . .
6459#-----------------------------------------------------
6460
6461router
6462end
6463
6464#------------------------------------------------------------
6465# Plowing (restored in magic 8.2, need to fill this section)
6466#------------------------------------------------------------
6467
6468plowing
6469end
6470
6471#-----------------------------------------------------------------
6472# No special plot layers defined (use default PNM color choices)
6473#-----------------------------------------------------------------
6474
6475plot
6476 style pnm
6477 default
6478 draw fillblock no_color_at_all
6479 draw nwell cwell
6480end
6481