flow/CLA64/tb.sv

module tb ();

   logic [63:0] A;
   logic [63:0] B;
   logic 	op;
   logic [63:0] Sum;
   
   logic 	clk;   
   
   integer 	handle3;
   integer 	desc3;   
   
   // instantiate device under test
   cla64 dut (Sum, A, B, op);
   
   // generate clock
   always 
     begin
	clk = 1; #10; clk = 0; #10;
     end
   
   initial
     begin
	handle3 = $fopen("test.out");
	#200 $finish;		
     end
   
   always 
     begin
	desc3 = handle3;
	#5 $fdisplay(desc3, "%h %h %b || %h", 
		     A, B, op, Sum);
     end   
   
   initial
     begin
	#0   A = 64'h0;
	#0   B = 64'h0;
	#0   op = 1'b0;	
	
	#20  A = $random;	
	#0   B = $random;	

	#20  A = $random;	
	#0   B = $random;	

	#20  A = $random;	
	#0   B = $random;	

	#20  A = $random;	
	#0   B = $random;	

	#20  A = $random;	
	#0   B = $random;	

	#20  A = $random;	
	#0   B = $random;	

	#20  A = $random;	
	#0   B = $random;	

	#20  A = $random;	
	#0   B = $random;	

	#20  A = $random;	
	#0   B = $random;		
     end
   
endmodule // tb