blob: 39435143a8b12f21c7ee338046e3fb64bbb91dae [file] [log] [blame]
module tb ();
logic [15:0] result;
logic [7:0] a;
logic [7:0] b;
logic reset;
logic clk;
integer handle3;
integer desc3;
// instantiate device under test
mac dut (result, a, b, reset, clk);
// generate clock
always
begin
clk = 1; #10; clk = 0; #10;
end
initial
begin
handle3 = $fopen("test.out");
#200 $finish;
end
always
begin
desc3 = handle3;
#5 $fdisplay(desc3, "%h %h || %h",
a, b, result);
end
initial
begin
#0 a = 16'h0;
#0 b = 16'h0;
#0 reset = 1'b0;
#15 reset = 1'b1;
#20 a = $random;
#0 b = $random;
#20 a = $random;
#0 b = $random;
#20 a = $random;
#0 b = $random;
#20 a = $random;
#0 b = $random;
#20 a = $random;
#0 b = $random;
#20 a = $random;
#0 b = $random;
#20 a = $random;
#0 b = $random;
#20 a = $random;
#0 b = $random;
#20 a = $random;
#0 b = $random;
end
endmodule // tb