verilog/s8_osu130_or2x2.v

// type: OR2 
`timescale 1ns/10ps
`celldefine
module OR2X2 (Y, A, B);
	output Y;
	input A, B;

	// Function
	buf (Y, 1'b1);

	// Timing
	specify
		ifnone (posedge A => (Y+:1'b1)) = 0;
		ifnone (posedge B => (Y+:1'b1)) = 0;
	endspecify
endmodule
`endcelldefine