verilog/s8_osu130_dffxl.v

// type: DFF 
`timescale 1ns/10ps
`celldefine
module DFFXL (Q, QN, D, CK);
	output Q, QN;
	input D, CK;
	reg notifier;
	wire delayed_D, delayed_CK;

	// Function
	wire delayed_D__bar, int_fwire_0, int_fwire_d;
	wire int_fwire_IQ, int_fwire_IQN, xcr_0;

	not (delayed_D__bar, delayed_D);
	and (int_fwire_0, delayed_D__bar, int_fwire_IQ);
	or (int_fwire_d, delayed_D, int_fwire_0);
	altos_dff_err (xcr_0, delayed_CK, int_fwire_d);
	altos_dff (int_fwire_IQ, notifier, delayed_CK, int_fwire_d, xcr_0);
	buf (Q, int_fwire_IQ);
	not (int_fwire_IQN, int_fwire_IQ);
	buf (QN, int_fwire_IQN);

	// Timing
	specify
		(posedge CK => (Q+:((D) || (!D && int_fwire_IQ)))) = 0;
		(posedge CK => (QN-:((D) || (!D && int_fwire_IQ)))) = 0;
		$setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
		$setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
		$width (posedge CK &&& D, 0, 0, notifier);
		$width (negedge CK &&& D, 0, 0, notifier);
	endspecify
endmodule
`endcelldefine