blob: 9395a2f89ff758a74f66eb931c53ab1ec19837b3 [file] [log] [blame]
// type: AOI21
`timescale 1ns/10ps
`celldefine
module AOI21XL (Y, A0, A1, B0);
output Y;
input A0, A1, B0;
// Function
wire A0__bar, A1__bar, B0__bar;
wire int_fwire_0, int_fwire_1;
not (B0__bar, B0);
not (A1__bar, A1);
and (int_fwire_0, A1__bar, B0__bar);
not (A0__bar, A0);
and (int_fwire_1, A0__bar, B0__bar);
or (Y, int_fwire_1, int_fwire_0);
// Timing
specify
(A0 => Y) = 0;
(A1 => Y) = 0;
if ((A0 & ~A1))
(B0 => Y) = 0;
if ((~A0 & A1))
(B0 => Y) = 0;
if ((~A0 & ~A1))
(B0 => Y) = 0;
ifnone (B0 => Y) = 0;
endspecify
endmodule
`endcelldefine