blob: 4844c70d43e92e30b15db4a453a22aa4e77a8607 [file] [log] [blame]
// type: ADDH
`timescale 1ns/10ps
`celldefine
module ADDHXL (CO, S, A, B);
output CO, S;
input A, B;
// Function
wire A__bar, B__bar, int_fwire_0;
wire int_fwire_1;
and (CO, A, B);
not (A__bar, A);
and (int_fwire_0, A__bar, B);
not (B__bar, B);
and (int_fwire_1, A, B__bar);
or (S, int_fwire_1, int_fwire_0);
// Timing
specify
(A => CO) = 0;
(B => CO) = 0;
if (~B)
(A => S) = 0;
if (B)
(A => S) = 0;
if (~A)
(B => S) = 0;
if (A)
(B => S) = 0;
endspecify
endmodule
`endcelldefine