verilog/s8_osu130_addfxl.v

// type: ADDF 
`timescale 1ns/10ps
`celldefine
module ADDFXL (CO, S, A, B, CI);
	output CO, S;
	input A, B, CI;

	// Function
	or (CO, B, CI);
	buf (S, 1'b1);

	// Timing
	specify
		if ((B & ~CI))
			(posedge A => (CO+:1'b1)) = 0;
		if ((~B & CI))
			(posedge A => (CO+:1'b1)) = 0;
		ifnone (posedge A => (CO+:1'b1)) = 0;
		if ((A & ~CI))
			(B => CO) = 0;
		if ((~A & CI))
			(posedge B => (CO+:1'b1)) = 0;
		if ((~A & ~CI))
			(negedge B => (CO+:1'b0)) = 0;
		ifnone (B => CO) = 0;
		if ((A & ~B))
			(CI => CO) = 0;
		if ((~A & B))
			(posedge CI => (CO+:1'b1)) = 0;
		if ((~A & ~B))
			(negedge CI => (CO+:1'b0)) = 0;
		ifnone (CI => CO) = 0;
		if ((B & CI))
			(posedge A => (S+:1'b1)) = 0;
		if ((~B & ~CI))
			(posedge A => (S+:1'b1)) = 0;
		ifnone (posedge A => (S+:1'b1)) = 0;
		if ((A & CI))
			(posedge B => (S+:1'b1)) = 0;
		if ((~A & ~CI))
			(posedge B => (S+:1'b1)) = 0;
		ifnone (posedge B => (S+:1'b1)) = 0;
		if ((A & B))
			(posedge CI => (S+:1'b1)) = 0;
		if ((~A & ~B))
			(posedge CI => (S+:1'b1)) = 0;
		ifnone (posedge CI => (S+:1'b1)) = 0;
	endspecify
endmodule
`endcelldefine