Split verilog
diff --git a/verilog/s8_osu130_nand3x1.v b/verilog/s8_osu130_nand3x1.v
new file mode 100644
index 0000000..f0f2dbc
--- /dev/null
+++ b/verilog/s8_osu130_nand3x1.v
@@ -0,0 +1,24 @@
+// type: NAND3
+`timescale 1ns/10ps
+`celldefine
+module NAND3X1 (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
