Split verilog
diff --git a/verilog/s8_osu130_addfx1.v b/verilog/s8_osu130_addfx1.v
new file mode 100644
index 0000000..5b8a214
--- /dev/null
+++ b/verilog/s8_osu130_addfx1.v
@@ -0,0 +1,74 @@
+// type: ADDF
+`timescale 1ns/10ps
+`celldefine
+module ADDFX1 (CO, S, A, B, CI);
+ output CO, S;
+ input A, B, CI;
+
+ // Function
+ wire A__bar, B__bar, CI__bar;
+ wire int_fwire_0, int_fwire_1, int_fwire_2;
+ wire int_fwire_3, int_fwire_4, int_fwire_5;
+ wire int_fwire_6;
+
+ and (int_fwire_0, B, CI);
+ and (int_fwire_1, A, CI);
+ and (int_fwire_2, A, B);
+ or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
+ not (B__bar, B);
+ not (A__bar, A);
+ and (int_fwire_3, A__bar, B__bar, CI);
+ not (CI__bar, CI);
+ and (int_fwire_4, A__bar, B, CI__bar);
+ and (int_fwire_5, A, B__bar, CI__bar);
+ and (int_fwire_6, A, B, CI);
+ or (S, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3);
+
+ // Timing
+ specify
+ if ((B & ~CI))
+ (A => CO) = 0;
+ if ((~B & CI))
+ (A => CO) = 0;
+ ifnone (A => CO) = 0;
+ if ((A & ~CI))
+ (B => CO) = 0;
+ if ((~A & CI))
+ (B => CO) = 0;
+ ifnone (B => CO) = 0;
+ if ((A & ~B))
+ (CI => CO) = 0;
+ if ((~A & B))
+ (CI => CO) = 0;
+ ifnone (CI => CO) = 0;
+ if ((B & CI))
+ (A => S) = 0;
+ if ((~B & ~CI))
+ (A => S) = 0;
+ ifnone (A => S) = 0;
+ if ((B & ~CI))
+ (A => S) = 0;
+ if ((~B & CI))
+ (A => S) = 0;
+ if ((A & CI))
+ (B => S) = 0;
+ if ((~A & ~CI))
+ (B => S) = 0;
+ ifnone (B => S) = 0;
+ if ((A & ~CI))
+ (B => S) = 0;
+ if ((~A & CI))
+ (B => S) = 0;
+ if ((A & B))
+ (CI => S) = 0;
+ if ((~A & ~B))
+ (CI => S) = 0;
+ ifnone (CI => S) = 0;
+ if ((A & ~B))
+ (CI => S) = 0;
+ if ((~A & B))
+ (CI => S) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_addfxl.v b/verilog/s8_osu130_addfxl.v
new file mode 100644
index 0000000..05dcac7
--- /dev/null
+++ b/verilog/s8_osu130_addfxl.v
@@ -0,0 +1,51 @@
+// type: ADDF
+`timescale 1ns/10ps
+`celldefine
+module ADDFXL (CO, S, A, B, CI);
+ output CO, S;
+ input A, B, CI;
+
+ // Function
+ or (CO, B, CI);
+ buf (S, 1'b1);
+
+ // Timing
+ specify
+ if ((B & ~CI))
+ (posedge A => (CO+:1'b1)) = 0;
+ if ((~B & CI))
+ (posedge A => (CO+:1'b1)) = 0;
+ ifnone (posedge A => (CO+:1'b1)) = 0;
+ if ((A & ~CI))
+ (B => CO) = 0;
+ if ((~A & CI))
+ (posedge B => (CO+:1'b1)) = 0;
+ if ((~A & ~CI))
+ (negedge B => (CO+:1'b0)) = 0;
+ ifnone (B => CO) = 0;
+ if ((A & ~B))
+ (CI => CO) = 0;
+ if ((~A & B))
+ (posedge CI => (CO+:1'b1)) = 0;
+ if ((~A & ~B))
+ (negedge CI => (CO+:1'b0)) = 0;
+ ifnone (CI => CO) = 0;
+ if ((B & CI))
+ (posedge A => (S+:1'b1)) = 0;
+ if ((~B & ~CI))
+ (posedge A => (S+:1'b1)) = 0;
+ ifnone (posedge A => (S+:1'b1)) = 0;
+ if ((A & CI))
+ (posedge B => (S+:1'b1)) = 0;
+ if ((~A & ~CI))
+ (posedge B => (S+:1'b1)) = 0;
+ ifnone (posedge B => (S+:1'b1)) = 0;
+ if ((A & B))
+ (posedge CI => (S+:1'b1)) = 0;
+ if ((~A & ~B))
+ (posedge CI => (S+:1'b1)) = 0;
+ ifnone (posedge CI => (S+:1'b1)) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_addhx1.v b/verilog/s8_osu130_addhx1.v
new file mode 100644
index 0000000..f9f0c26
--- /dev/null
+++ b/verilog/s8_osu130_addhx1.v
@@ -0,0 +1,27 @@
+// type: ADDH
+`timescale 1ns/10ps
+`celldefine
+module ADDHX1 (CO, S, A, B);
+ output CO, S;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ and (CO, A, B);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (S, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => CO) = 0;
+ (B => CO) = 0;
+ ifnone (posedge A => (S+:1'b1)) = 0;
+ (A => S) = 0;
+ ifnone (posedge B => (S+:1'b1)) = 0;
+ (B => S) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_addhxl.v b/verilog/s8_osu130_addhxl.v
new file mode 100644
index 0000000..4844c70
--- /dev/null
+++ b/verilog/s8_osu130_addhxl.v
@@ -0,0 +1,34 @@
+// type: ADDH
+`timescale 1ns/10ps
+`celldefine
+module ADDHXL (CO, S, A, B);
+ output CO, S;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ and (CO, A, B);
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B);
+ not (B__bar, B);
+ and (int_fwire_1, A, B__bar);
+ or (S, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A => CO) = 0;
+ (B => CO) = 0;
+ if (~B)
+ (A => S) = 0;
+ if (B)
+ (A => S) = 0;
+ if (~A)
+ (B => S) = 0;
+ if (A)
+ (B => S) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_and2x1.v b/verilog/s8_osu130_and2x1.v
new file mode 100644
index 0000000..85562b5
--- /dev/null
+++ b/verilog/s8_osu130_and2x1.v
@@ -0,0 +1,18 @@
+// type: AND2
+`timescale 1ns/10ps
+`celldefine
+module AND2X1 (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_and2x2.v b/verilog/s8_osu130_and2x2.v
new file mode 100644
index 0000000..5ee348a
--- /dev/null
+++ b/verilog/s8_osu130_and2x2.v
@@ -0,0 +1,18 @@
+// type: AND2
+`timescale 1ns/10ps
+`celldefine
+module AND2X2 (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_and2x4.v b/verilog/s8_osu130_and2x4.v
new file mode 100644
index 0000000..38b6682
--- /dev/null
+++ b/verilog/s8_osu130_and2x4.v
@@ -0,0 +1,18 @@
+// type: AND2
+`timescale 1ns/10ps
+`celldefine
+module AND2X4 (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_and2x8.v b/verilog/s8_osu130_and2x8.v
new file mode 100644
index 0000000..ed2e119
--- /dev/null
+++ b/verilog/s8_osu130_and2x8.v
@@ -0,0 +1,18 @@
+// type: AND2
+`timescale 1ns/10ps
+`celldefine
+module AND2X8 (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_and2xl.v b/verilog/s8_osu130_and2xl.v
new file mode 100644
index 0000000..201e4bd
--- /dev/null
+++ b/verilog/s8_osu130_and2xl.v
@@ -0,0 +1,18 @@
+// type: AND2
+`timescale 1ns/10ps
+`celldefine
+module AND2XL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ and (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_and3xl.v b/verilog/s8_osu130_and3xl.v
new file mode 100644
index 0000000..86f303e
--- /dev/null
+++ b/verilog/s8_osu130_and3xl.v
@@ -0,0 +1,24 @@
+// type: AND3
+`timescale 1ns/10ps
+`celldefine
+module AND3XL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_ant.v b/verilog/s8_osu130_ant.v
new file mode 100644
index 0000000..472073b
--- /dev/null
+++ b/verilog/s8_osu130_ant.v
@@ -0,0 +1,11 @@
+// type: ANT
+`timescale 1ns/10ps
+`celldefine
+module ANT (A);
+ input A;
+ // Timing
+ specify
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_aoi21xl.v b/verilog/s8_osu130_aoi21xl.v
new file mode 100644
index 0000000..9395a2f
--- /dev/null
+++ b/verilog/s8_osu130_aoi21xl.v
@@ -0,0 +1,33 @@
+// type: AOI21
+`timescale 1ns/10ps
+`celldefine
+module AOI21XL (Y, A0, A1, B0);
+ output Y;
+ input A0, A1, B0;
+
+ // Function
+ wire A0__bar, A1__bar, B0__bar;
+ wire int_fwire_0, int_fwire_1;
+
+ not (B0__bar, B0);
+ not (A1__bar, A1);
+ and (int_fwire_0, A1__bar, B0__bar);
+ not (A0__bar, A0);
+ and (int_fwire_1, A0__bar, B0__bar);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ (A0 => Y) = 0;
+ (A1 => Y) = 0;
+ if ((A0 & ~A1))
+ (B0 => Y) = 0;
+ if ((~A0 & A1))
+ (B0 => Y) = 0;
+ if ((~A0 & ~A1))
+ (B0 => Y) = 0;
+ ifnone (B0 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_bufx1.v b/verilog/s8_osu130_bufx1.v
new file mode 100644
index 0000000..0e39291
--- /dev/null
+++ b/verilog/s8_osu130_bufx1.v
@@ -0,0 +1,17 @@
+// type: BUF
+`timescale 1ns/10ps
+`celldefine
+module BUFX1 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_bufx2.v b/verilog/s8_osu130_bufx2.v
new file mode 100644
index 0000000..35126a6
--- /dev/null
+++ b/verilog/s8_osu130_bufx2.v
@@ -0,0 +1,17 @@
+// type: BUF
+`timescale 1ns/10ps
+`celldefine
+module BUFX2 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_bufx4.v b/verilog/s8_osu130_bufx4.v
new file mode 100644
index 0000000..31285b4
--- /dev/null
+++ b/verilog/s8_osu130_bufx4.v
@@ -0,0 +1,17 @@
+// type: BUF
+`timescale 1ns/10ps
+`celldefine
+module BUFX4 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_bufx6.v b/verilog/s8_osu130_bufx6.v
new file mode 100644
index 0000000..926c81b
--- /dev/null
+++ b/verilog/s8_osu130_bufx6.v
@@ -0,0 +1,17 @@
+// type: BUF
+`timescale 1ns/10ps
+`celldefine
+module BUFX6 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_bufx8.v b/verilog/s8_osu130_bufx8.v
new file mode 100644
index 0000000..d81c32f
--- /dev/null
+++ b/verilog/s8_osu130_bufx8.v
@@ -0,0 +1,17 @@
+// type: BUF
+`timescale 1ns/10ps
+`celldefine
+module BUFX8 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_bufxl.v b/verilog/s8_osu130_bufxl.v
new file mode 100644
index 0000000..6dde6e9
--- /dev/null
+++ b/verilog/s8_osu130_bufxl.v
@@ -0,0 +1,17 @@
+// type: BUF
+`timescale 1ns/10ps
+`celldefine
+module BUFXL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_clkbufx1.v b/verilog/s8_osu130_clkbufx1.v
new file mode 100644
index 0000000..9550a02
--- /dev/null
+++ b/verilog/s8_osu130_clkbufx1.v
@@ -0,0 +1,17 @@
+// type: CLKBUF
+`timescale 1ns/10ps
+`celldefine
+module CLKBUFX1 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_clkinvx1.v b/verilog/s8_osu130_clkinvx1.v
new file mode 100644
index 0000000..c0fb04b
--- /dev/null
+++ b/verilog/s8_osu130_clkinvx1.v
@@ -0,0 +1,17 @@
+// type: CLKINV
+`timescale 1ns/10ps
+`celldefine
+module CLKINVX1 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_clkinvx2.v b/verilog/s8_osu130_clkinvx2.v
new file mode 100644
index 0000000..9e48ff4
--- /dev/null
+++ b/verilog/s8_osu130_clkinvx2.v
@@ -0,0 +1,17 @@
+// type: CLKINV
+`timescale 1ns/10ps
+`celldefine
+module CLKINVX2 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_clkinvx4.v b/verilog/s8_osu130_clkinvx4.v
new file mode 100644
index 0000000..6817a57
--- /dev/null
+++ b/verilog/s8_osu130_clkinvx4.v
@@ -0,0 +1,17 @@
+// type: CLKINV
+`timescale 1ns/10ps
+`celldefine
+module CLKINVX4 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_dffnxl.v b/verilog/s8_osu130_dffnxl.v
new file mode 100644
index 0000000..5fedeef
--- /dev/null
+++ b/verilog/s8_osu130_dffnxl.v
@@ -0,0 +1,34 @@
+// type: DFFN
+`timescale 1ns/10ps
+`celldefine
+module DFFNXL (Q, QN, D, CK);
+ output Q, QN;
+ input D, CK;
+ reg notifier;
+ wire delayed_D, delayed_CK;
+
+ // Function
+ wire int_fwire_clk, int_fwire_IQ, int_fwire_IQN;
+ wire xcr_0;
+
+ not (int_fwire_clk, delayed_CK);
+ altos_dff_err (xcr_0, int_fwire_clk, delayed_D);
+ altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0);
+ buf (Q, int_fwire_IQ);
+ not (int_fwire_IQN, int_fwire_IQ);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+ specify
+ (negedge CK => (Q+:D)) = 0;
+ (negedge CK => (QN-:D)) = 0;
+ $setuphold (negedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $setuphold (negedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $width (posedge CK &&& D, 0, 0, notifier);
+ $width (negedge CK &&& D, 0, 0, notifier);
+ $width (posedge CK &&& ~D, 0, 0, notifier);
+ $width (negedge CK &&& ~D, 0, 0, notifier);
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_dffrxl.v b/verilog/s8_osu130_dffrxl.v
new file mode 100644
index 0000000..230c134
--- /dev/null
+++ b/verilog/s8_osu130_dffrxl.v
@@ -0,0 +1,66 @@
+// type: DFFR
+`timescale 1ns/10ps
+`celldefine
+module DFFRXL (Q, QN, D, RN, CK);
+ output Q, QN;
+ input D, RN, CK;
+ reg notifier;
+ wire delayed_D, delayed_CK;
+
+ // Function
+ wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
+ wire xcr_0;
+
+ not (int_fwire_r, RN);
+ altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
+ altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
+ buf (Q, int_fwire_IQ);
+ not (int_fwire_IQN, int_fwire_IQ);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, D__bar;
+
+
+ // Additional timing gates
+ and (adacond0, D, RN);
+ not (D__bar, D);
+ and (adacond1, D__bar, RN);
+
+ specify
+ if (CK)
+ (negedge RN => (Q+:1'b0)) = 0;
+ if ((~CK & D))
+ (negedge RN => (Q+:1'b0)) = 0;
+ if ((~CK & ~D))
+ (negedge RN => (Q+:1'b0)) = 0;
+ ifnone (negedge RN => (Q+:1'b0)) = 0;
+ (posedge CK => (Q+:D)) = 0;
+ if (CK)
+ (negedge RN => (QN-:1'b0)) = 0;
+ if ((~CK & D))
+ (negedge RN => (QN-:1'b0)) = 0;
+ if ((~CK & ~D))
+ (negedge RN => (QN-:1'b0)) = 0;
+ ifnone (negedge RN => (QN-:1'b0)) = 0;
+ (posedge CK => (QN-:D)) = 0;
+ $setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
+ $recovery (posedge RN, posedge CK, 0, notifier);
+ $hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
+ $hold (posedge CK, posedge RN, 0, notifier);
+ $width (negedge RN &&& CK, 0, 0, notifier);
+ $width (negedge RN &&& ~CK, 0, 0, notifier);
+ $width (posedge CK &&& adacond0, 0, 0, notifier);
+ $width (negedge CK &&& adacond0, 0, 0, notifier);
+ $width (posedge CK &&& adacond1, 0, 0, notifier);
+ $width (negedge CK &&& adacond1, 0, 0, notifier);
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_dffsxl.v b/verilog/s8_osu130_dffsxl.v
new file mode 100644
index 0000000..45f9995
--- /dev/null
+++ b/verilog/s8_osu130_dffsxl.v
@@ -0,0 +1,66 @@
+// type: DFFS
+`timescale 1ns/10ps
+`celldefine
+module DFFSXL (Q, QN, D, SN, CK);
+ output Q, QN;
+ input D, SN, CK;
+ reg notifier;
+ wire delayed_D, delayed_CK;
+
+ // Function
+ wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
+ wire xcr_0;
+
+ not (int_fwire_s, SN);
+ altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
+ altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
+ buf (Q, int_fwire_IQ);
+ not (int_fwire_IQN, int_fwire_IQ);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+
+ // Additional timing wires
+ wire adacond0, adacond1, D__bar;
+
+
+ // Additional timing gates
+ and (adacond0, D, SN);
+ not (D__bar, D);
+ and (adacond1, D__bar, SN);
+
+ specify
+ if (CK)
+ (negedge SN => (Q+:1'b1)) = 0;
+ if ((~CK & D))
+ (negedge SN => (Q+:1'b1)) = 0;
+ if ((~CK & ~D))
+ (negedge SN => (Q+:1'b1)) = 0;
+ ifnone (negedge SN => (Q+:1'b1)) = 0;
+ (posedge CK => (Q+:D)) = 0;
+ if (CK)
+ (negedge SN => (QN-:1'b1)) = 0;
+ if ((~CK & D))
+ (negedge SN => (QN-:1'b1)) = 0;
+ if ((~CK & ~D))
+ (negedge SN => (QN-:1'b1)) = 0;
+ ifnone (negedge SN => (QN-:1'b1)) = 0;
+ (posedge CK => (QN-:D)) = 0;
+ $setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
+ $recovery (posedge SN, posedge CK, 0, notifier);
+ $hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
+ $hold (posedge CK, posedge SN, 0, notifier);
+ $width (negedge SN &&& CK, 0, 0, notifier);
+ $width (negedge SN &&& ~CK, 0, 0, notifier);
+ $width (posedge CK &&& adacond0, 0, 0, notifier);
+ $width (negedge CK &&& adacond0, 0, 0, notifier);
+ $width (posedge CK &&& adacond1, 0, 0, notifier);
+ $width (negedge CK &&& adacond1, 0, 0, notifier);
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_dffxl.v b/verilog/s8_osu130_dffxl.v
new file mode 100644
index 0000000..01db9d7
--- /dev/null
+++ b/verilog/s8_osu130_dffxl.v
@@ -0,0 +1,34 @@
+// type: DFF
+`timescale 1ns/10ps
+`celldefine
+module DFFXL (Q, QN, D, CK);
+ output Q, QN;
+ input D, CK;
+ reg notifier;
+ wire delayed_D, delayed_CK;
+
+ // Function
+ wire delayed_D__bar, int_fwire_0, int_fwire_d;
+ wire int_fwire_IQ, int_fwire_IQN, xcr_0;
+
+ not (delayed_D__bar, delayed_D);
+ and (int_fwire_0, delayed_D__bar, int_fwire_IQ);
+ or (int_fwire_d, delayed_D, int_fwire_0);
+ altos_dff_err (xcr_0, delayed_CK, int_fwire_d);
+ altos_dff (int_fwire_IQ, notifier, delayed_CK, int_fwire_d, xcr_0);
+ buf (Q, int_fwire_IQ);
+ not (int_fwire_IQN, int_fwire_IQ);
+ buf (QN, int_fwire_IQN);
+
+ // Timing
+ specify
+ (posedge CK => (Q+:((D) || (!D && int_fwire_IQ)))) = 0;
+ (posedge CK => (QN-:((D) || (!D && int_fwire_IQ)))) = 0;
+ $setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
+ $width (posedge CK &&& D, 0, 0, notifier);
+ $width (negedge CK &&& D, 0, 0, notifier);
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_dly1.v b/verilog/s8_osu130_dly1.v
new file mode 100644
index 0000000..805e87b
--- /dev/null
+++ b/verilog/s8_osu130_dly1.v
@@ -0,0 +1,17 @@
+// type: DLY1
+`timescale 1ns/10ps
+`celldefine
+module DLY1 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_dly2.v b/verilog/s8_osu130_dly2.v
new file mode 100644
index 0000000..dea6e9f
--- /dev/null
+++ b/verilog/s8_osu130_dly2.v
@@ -0,0 +1,17 @@
+// type: DLY2
+`timescale 1ns/10ps
+`celldefine
+module DLY2 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_dly3.v b/verilog/s8_osu130_dly3.v
new file mode 100644
index 0000000..c9b2116
--- /dev/null
+++ b/verilog/s8_osu130_dly3.v
@@ -0,0 +1,17 @@
+// type: DLY3
+`timescale 1ns/10ps
+`celldefine
+module DLY3 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_dly4.v b/verilog/s8_osu130_dly4.v
new file mode 100644
index 0000000..a703499
--- /dev/null
+++ b/verilog/s8_osu130_dly4.v
@@ -0,0 +1,17 @@
+// type: DLY4
+`timescale 1ns/10ps
+`celldefine
+module DLY4 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ buf (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_invx1.v b/verilog/s8_osu130_invx1.v
new file mode 100644
index 0000000..16b0250
--- /dev/null
+++ b/verilog/s8_osu130_invx1.v
@@ -0,0 +1,17 @@
+// type: INV
+`timescale 1ns/10ps
+`celldefine
+module INVX1 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_invx10.v b/verilog/s8_osu130_invx10.v
new file mode 100644
index 0000000..4dd24fc
--- /dev/null
+++ b/verilog/s8_osu130_invx10.v
@@ -0,0 +1,17 @@
+// type: INV
+`timescale 1ns/10ps
+`celldefine
+module INVX10 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_invx2.v b/verilog/s8_osu130_invx2.v
new file mode 100644
index 0000000..e259cd7
--- /dev/null
+++ b/verilog/s8_osu130_invx2.v
@@ -0,0 +1,17 @@
+// type: INV
+`timescale 1ns/10ps
+`celldefine
+module INVX2 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_invx3.v b/verilog/s8_osu130_invx3.v
new file mode 100644
index 0000000..34cd10d
--- /dev/null
+++ b/verilog/s8_osu130_invx3.v
@@ -0,0 +1,17 @@
+// type: INV
+`timescale 1ns/10ps
+`celldefine
+module INVX3 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_invx4.v b/verilog/s8_osu130_invx4.v
new file mode 100644
index 0000000..ec6995a
--- /dev/null
+++ b/verilog/s8_osu130_invx4.v
@@ -0,0 +1,17 @@
+// type: INV
+`timescale 1ns/10ps
+`celldefine
+module INVX4 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_invx6.v b/verilog/s8_osu130_invx6.v
new file mode 100644
index 0000000..7f3da23
--- /dev/null
+++ b/verilog/s8_osu130_invx6.v
@@ -0,0 +1,17 @@
+// type: INV
+`timescale 1ns/10ps
+`celldefine
+module INVX6 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_invx8.v b/verilog/s8_osu130_invx8.v
new file mode 100644
index 0000000..f5cf36a
--- /dev/null
+++ b/verilog/s8_osu130_invx8.v
@@ -0,0 +1,17 @@
+// type: INV
+`timescale 1ns/10ps
+`celldefine
+module INVX8 (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_invxl.v b/verilog/s8_osu130_invxl.v
new file mode 100644
index 0000000..1a3084e
--- /dev/null
+++ b/verilog/s8_osu130_invxl.v
@@ -0,0 +1,17 @@
+// type: INV
+`timescale 1ns/10ps
+`celldefine
+module INVXL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ not (Y, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_nand2x1.v b/verilog/s8_osu130_nand2x1.v
new file mode 100644
index 0000000..a44c3a3
--- /dev/null
+++ b/verilog/s8_osu130_nand2x1.v
@@ -0,0 +1,22 @@
+// type: NAND2
+`timescale 1ns/10ps
+`celldefine
+module NAND2X1 (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_nand2xl.v b/verilog/s8_osu130_nand2xl.v
new file mode 100644
index 0000000..7e9af58
--- /dev/null
+++ b/verilog/s8_osu130_nand2xl.v
@@ -0,0 +1,22 @@
+// type: NAND2
+`timescale 1ns/10ps
+`celldefine
+module NAND2XL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_nand3x1.v b/verilog/s8_osu130_nand3x1.v
new file mode 100644
index 0000000..f0f2dbc
--- /dev/null
+++ b/verilog/s8_osu130_nand3x1.v
@@ -0,0 +1,24 @@
+// type: NAND3
+`timescale 1ns/10ps
+`celldefine
+module NAND3X1 (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_nand3xl.v b/verilog/s8_osu130_nand3xl.v
new file mode 100644
index 0000000..f221c67
--- /dev/null
+++ b/verilog/s8_osu130_nand3xl.v
@@ -0,0 +1,24 @@
+// type: NAND3
+`timescale 1ns/10ps
+`celldefine
+module NAND3XL (Y, A, B, C);
+ output Y;
+ input A, B, C;
+
+ // Function
+ wire A__bar, B__bar, C__bar;
+
+ not (C__bar, C);
+ not (B__bar, B);
+ not (A__bar, A);
+ or (Y, A__bar, B__bar, C__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ (C => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_nor2x1.v b/verilog/s8_osu130_nor2x1.v
new file mode 100644
index 0000000..836dbf6
--- /dev/null
+++ b/verilog/s8_osu130_nor2x1.v
@@ -0,0 +1,22 @@
+// type: NOR2
+`timescale 1ns/10ps
+`celldefine
+module NOR2X1 (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_nor2xl.v b/verilog/s8_osu130_nor2xl.v
new file mode 100644
index 0000000..6469c1a
--- /dev/null
+++ b/verilog/s8_osu130_nor2xl.v
@@ -0,0 +1,22 @@
+// type: NOR2
+`timescale 1ns/10ps
+`celldefine
+module NOR2XL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (Y, A__bar, B__bar);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_oai21xl.v b/verilog/s8_osu130_oai21xl.v
new file mode 100644
index 0000000..5a6a646
--- /dev/null
+++ b/verilog/s8_osu130_oai21xl.v
@@ -0,0 +1,32 @@
+// type: OAI21
+`timescale 1ns/10ps
+`celldefine
+module OAI21XL (Y, A0, A1, B0);
+ output Y;
+ input A0, A1, B0;
+
+ // Function
+ wire A0__bar, A1__bar, B0__bar;
+ wire int_fwire_0;
+
+ not (B0__bar, B0);
+ not (A1__bar, A1);
+ not (A0__bar, A0);
+ and (int_fwire_0, A0__bar, A1__bar);
+ or (Y, int_fwire_0, B0__bar);
+
+ // Timing
+ specify
+ (A0 => Y) = 0;
+ (A1 => Y) = 0;
+ if ((A0 & A1))
+ (B0 => Y) = 0;
+ if ((A0 & ~A1))
+ (B0 => Y) = 0;
+ if ((~A0 & A1))
+ (B0 => Y) = 0;
+ ifnone (B0 => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_or2x1.v b/verilog/s8_osu130_or2x1.v
new file mode 100644
index 0000000..75d0287
--- /dev/null
+++ b/verilog/s8_osu130_or2x1.v
@@ -0,0 +1,18 @@
+// type: OR2
+`timescale 1ns/10ps
+`celldefine
+module OR2X1 (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ or (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_or2x2.v b/verilog/s8_osu130_or2x2.v
new file mode 100644
index 0000000..0a86467
--- /dev/null
+++ b/verilog/s8_osu130_or2x2.v
@@ -0,0 +1,18 @@
+// type: OR2
+`timescale 1ns/10ps
+`celldefine
+module OR2X2 (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ buf (Y, 1'b1);
+
+ // Timing
+ specify
+ ifnone (posedge A => (Y+:1'b1)) = 0;
+ ifnone (posedge B => (Y+:1'b1)) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_or2x4.v b/verilog/s8_osu130_or2x4.v
new file mode 100644
index 0000000..92bbe0e
--- /dev/null
+++ b/verilog/s8_osu130_or2x4.v
@@ -0,0 +1,18 @@
+// type: OR2
+`timescale 1ns/10ps
+`celldefine
+module OR2X4 (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ or (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_or2xl.v b/verilog/s8_osu130_or2xl.v
new file mode 100644
index 0000000..524c5b0
--- /dev/null
+++ b/verilog/s8_osu130_or2xl.v
@@ -0,0 +1,18 @@
+// type: OR2
+`timescale 1ns/10ps
+`celldefine
+module OR2XL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ or (Y, A, B);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_tbufxl.v b/verilog/s8_osu130_tbufxl.v
new file mode 100644
index 0000000..7885ff8
--- /dev/null
+++ b/verilog/s8_osu130_tbufxl.v
@@ -0,0 +1,18 @@
+// type: TBUF
+`timescale 1ns/10ps
+`celldefine
+module TBUFXL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ bufif1 (Y, 1'b1, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (negedge A => (Y:1)) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_tiehi.v b/verilog/s8_osu130_tiehi.v
new file mode 100644
index 0000000..84f2164
--- /dev/null
+++ b/verilog/s8_osu130_tiehi.v
@@ -0,0 +1,15 @@
+// type: TIEHI
+`timescale 1ns/10ps
+`celldefine
+module TIEHI (Y);
+ output Y;
+
+ // Function
+ buf (Y, 1'b1);
+
+ // Timing
+ specify
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_tielo.v b/verilog/s8_osu130_tielo.v
new file mode 100644
index 0000000..f83e915
--- /dev/null
+++ b/verilog/s8_osu130_tielo.v
@@ -0,0 +1,15 @@
+// type: TIELO
+`timescale 1ns/10ps
+`celldefine
+module TIELO (Y);
+ output Y;
+
+ // Function
+ buf (Y, 1'b0);
+
+ // Timing
+ specify
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_tnbufxl.v b/verilog/s8_osu130_tnbufxl.v
new file mode 100644
index 0000000..f065eb1
--- /dev/null
+++ b/verilog/s8_osu130_tnbufxl.v
@@ -0,0 +1,18 @@
+// type: TNBUF
+`timescale 1ns/10ps
+`celldefine
+module TNBUFXL (Y, A);
+ output Y;
+ input A;
+
+ // Function
+ bufif0 (Y, 1'b1, A);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ (negedge A => (Y:1)) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_xnor2xl.v b/verilog/s8_osu130_xnor2xl.v
new file mode 100644
index 0000000..281f57d
--- /dev/null
+++ b/verilog/s8_osu130_xnor2xl.v
@@ -0,0 +1,31 @@
+// type: XNOR2
+`timescale 1ns/10ps
+`celldefine
+module XNOR2XL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, B__bar, int_fwire_0;
+ wire int_fwire_1;
+
+ not (B__bar, B);
+ not (A__bar, A);
+ and (int_fwire_0, A__bar, B__bar);
+ and (int_fwire_1, A, B);
+ or (Y, int_fwire_1, int_fwire_0);
+
+ // Timing
+ specify
+ if (B)
+ (A => Y) = 0;
+ if (~B)
+ (A => Y) = 0;
+ if (A)
+ (B => Y) = 0;
+ if (~A)
+ (B => Y) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
diff --git a/verilog/s8_osu130_xor2xl.v b/verilog/s8_osu130_xor2xl.v
new file mode 100644
index 0000000..4bddfac
--- /dev/null
+++ b/verilog/s8_osu130_xor2xl.v
@@ -0,0 +1,410 @@
+// type: XOR2
+`timescale 1ns/10ps
+`celldefine
+module XOR2XL (Y, A, B);
+ output Y;
+ input A, B;
+
+ // Function
+ wire A__bar, int_fwire_enable;
+
+ not (A__bar, A);
+ and (int_fwire_enable, A__bar, B);
+ bufif0 (Y, 1'b1, int_fwire_enable);
+
+ // Timing
+ specify
+ (A => Y) = 0;
+ ifnone (posedge A => (Y-:1'b0)) = 0;
+ (negedge A => (Y:1)) = 0;
+ ifnone (negedge B => (Y+:1'b0)) = 0;
+ (B => Y) = 0;
+ (posedge B => (Y:1)) = 0;
+ endspecify
+endmodule
+`endcelldefine
+
+
+`ifdef _udp_def_altos_latch_
+`else
+`define _udp_def_altos_latch_
+primitive altos_latch (q, v, clk, d);
+ output q;
+ reg q;
+ input v, clk, d;
+
+ table
+ * ? ? : ? : x;
+ ? 1 0 : ? : 0;
+ ? 1 1 : ? : 1;
+ ? x 0 : 0 : -;
+ ? x 1 : 1 : -;
+ ? 0 ? : ? : -;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_err_
+`else
+`define _udp_def_altos_dff_err_
+primitive altos_dff_err (q, clk, d);
+ output q;
+ reg q;
+ input clk, d;
+
+ table
+ (0x) ? : ? : 0;
+ (1x) ? : ? : 1;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_
+`else
+`define _udp_def_altos_dff_
+primitive altos_dff (q, v, clk, d, xcr);
+ output q;
+ reg q;
+ input v, clk, d, xcr;
+
+ table
+ * ? ? ? : ? : x;
+ ? (x1) 0 0 : ? : 0;
+ ? (x1) 1 0 : ? : 1;
+ ? (x1) 0 1 : 0 : 0;
+ ? (x1) 1 1 : 1 : 1;
+ ? (x1) ? x : ? : -;
+ ? (bx) 0 ? : 0 : -;
+ ? (bx) 1 ? : 1 : -;
+ ? (x0) b ? : ? : -;
+ ? (x0) ? x : ? : -;
+ ? (01) 0 ? : ? : 0;
+ ? (01) 1 ? : ? : 1;
+ ? (10) ? ? : ? : -;
+ ? b * ? : ? : -;
+ ? ? ? * : ? : -;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_err_
+`else
+`define _udp_def_altos_dff_r_err_
+primitive altos_dff_r_err (q, clk, d, r);
+ output q;
+ reg q;
+ input clk, d, r;
+
+ table
+ ? 0 (0x) : ? : -;
+ ? 0 (x0) : ? : -;
+ (0x) ? 0 : ? : 0;
+ (0x) 0 x : ? : 0;
+ (1x) ? 0 : ? : 1;
+ (1x) 0 x : ? : 1;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_r_
+`else
+`define _udp_def_altos_dff_r_
+primitive altos_dff_r (q, v, clk, d, r, xcr);
+ output q;
+ reg q;
+ input v, clk, d, r, xcr;
+
+ table
+ * ? ? ? ? : ? : x;
+ ? ? ? 1 ? : ? : 0;
+ ? b ? (1?) ? : 0 : -;
+ ? x 0 (1?) ? : 0 : -;
+ ? ? ? (10) ? : ? : -;
+ ? ? ? (x0) ? : ? : -;
+ ? ? ? (0x) ? : 0 : -;
+ ? (x1) 0 ? 0 : ? : 0;
+ ? (x1) 1 0 0 : ? : 1;
+ ? (x1) 0 ? 1 : 0 : 0;
+ ? (x1) 1 0 1 : 1 : 1;
+ ? (x1) ? ? x : ? : -;
+ ? (bx) 0 ? ? : 0 : -;
+ ? (bx) 1 0 ? : 1 : -;
+ ? (x0) 0 ? ? : ? : -;
+ ? (x0) 1 0 ? : ? : -;
+ ? (x0) ? 0 x : ? : -;
+ ? (01) 0 ? ? : ? : 0;
+ ? (01) 1 0 ? : ? : 1;
+ ? (10) ? ? ? : ? : -;
+ ? b * ? ? : ? : -;
+ ? ? ? ? * : ? : -;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_err_
+`else
+`define _udp_def_altos_dff_s_err_
+primitive altos_dff_s_err (q, clk, d, s);
+ output q;
+ reg q;
+ input clk, d, s;
+
+ table
+ ? 1 (0x) : ? : -;
+ ? 1 (x0) : ? : -;
+ (0x) ? 0 : ? : 0;
+ (0x) 1 x : ? : 0;
+ (1x) ? 0 : ? : 1;
+ (1x) 1 x : ? : 1;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_s_
+`else
+`define _udp_def_altos_dff_s_
+primitive altos_dff_s (q, v, clk, d, s, xcr);
+ output q;
+ reg q;
+ input v, clk, d, s, xcr;
+
+ table
+ * ? ? ? ? : ? : x;
+ ? ? ? 1 ? : ? : 1;
+ ? b ? (1?) ? : 1 : -;
+ ? x 1 (1?) ? : 1 : -;
+ ? ? ? (10) ? : ? : -;
+ ? ? ? (x0) ? : ? : -;
+ ? ? ? (0x) ? : 1 : -;
+ ? (x1) 0 0 0 : ? : 0;
+ ? (x1) 1 ? 0 : ? : 1;
+ ? (x1) 1 ? 1 : 1 : 1;
+ ? (x1) 0 0 1 : 0 : 0;
+ ? (x1) ? ? x : ? : -;
+ ? (bx) 1 ? ? : 1 : -;
+ ? (bx) 0 0 ? : 0 : -;
+ ? (x0) 1 ? ? : ? : -;
+ ? (x0) 0 0 ? : ? : -;
+ ? (x0) ? 0 x : ? : -;
+ ? (01) 1 ? ? : ? : 1;
+ ? (01) 0 0 ? : ? : 0;
+ ? (10) ? ? ? : ? : -;
+ ? b * ? ? : ? : -;
+ ? ? ? ? * : ? : -;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_err_
+`else
+`define _udp_def_altos_dff_sr_err_
+primitive altos_dff_sr_err (q, clk, d, s, r);
+ output q;
+ reg q;
+ input clk, d, s, r;
+
+ table
+ ? 1 (0x) ? : ? : -;
+ ? 0 ? (0x) : ? : -;
+ ? 0 ? (x0) : ? : -;
+ (0x) ? 0 0 : ? : 0;
+ (0x) 1 x 0 : ? : 0;
+ (0x) 0 0 x : ? : 0;
+ (1x) ? 0 0 : ? : 1;
+ (1x) 1 x 0 : ? : 1;
+ (1x) 0 0 x : ? : 1;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_0
+`else
+`define _udp_def_altos_dff_sr_0
+primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
+ output q;
+ reg q;
+ input v, clk, d, s, r, xcr;
+
+ table
+ // v, clk, d, s, r : q' : q;
+
+ * ? ? ? ? ? : ? : x;
+ ? ? ? ? 1 ? : ? : 0;
+ ? ? ? 1 0 ? : ? : 1;
+ ? b ? (1?) 0 ? : 1 : -;
+ ? x 1 (1?) 0 ? : 1 : -;
+ ? ? ? (10) 0 ? : ? : -;
+ ? ? ? (x0) 0 ? : ? : -;
+ ? ? ? (0x) 0 ? : 1 : -;
+ ? b ? 0 (1?) ? : 0 : -;
+ ? x 0 0 (1?) ? : 0 : -;
+ ? ? ? 0 (10) ? : ? : -;
+ ? ? ? 0 (x0) ? : ? : -;
+ ? ? ? 0 (0x) ? : 0 : -;
+ ? (x1) 0 0 ? 0 : ? : 0;
+ ? (x1) 1 ? 0 0 : ? : 1;
+ ? (x1) 0 0 ? 1 : 0 : 0;
+ ? (x1) 1 ? 0 1 : 1 : 1;
+ ? (x1) ? ? 0 x : ? : -;
+ ? (x1) ? 0 ? x : ? : -;
+ ? (1x) 0 0 ? ? : 0 : -;
+ ? (1x) 1 ? 0 ? : 1 : -;
+ ? (x0) 0 0 ? ? : ? : -;
+ ? (x0) 1 ? 0 ? : ? : -;
+ ? (x0) ? 0 0 x : ? : -;
+ ? (0x) 0 0 ? ? : 0 : -;
+ ? (0x) 1 ? 0 ? : 1 : -;
+ ? (01) 0 0 ? ? : ? : 0;
+ ? (01) 1 ? 0 ? : ? : 1;
+ ? (10) ? 0 ? ? : ? : -;
+ ? (10) ? ? 0 ? : ? : -;
+ ? b * 0 ? ? : ? : -;
+ ? b * ? 0 ? : ? : -;
+ ? ? ? ? ? * : ? : -;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_dff_sr_1
+`else
+`define _udp_def_altos_dff_sr_1
+primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
+ output q;
+ reg q;
+ input v, clk, d, s, r, xcr;
+
+ table
+ // v, clk, d, s, r : q' : q;
+
+ * ? ? ? ? ? : ? : x;
+ ? ? ? 0 1 ? : ? : 0;
+ ? ? ? 1 ? ? : ? : 1;
+ ? b ? (1?) 0 ? : 1 : -;
+ ? x 1 (1?) 0 ? : 1 : -;
+ ? ? ? (10) 0 ? : ? : -;
+ ? ? ? (x0) 0 ? : ? : -;
+ ? ? ? (0x) 0 ? : 1 : -;
+ ? b ? 0 (1?) ? : 0 : -;
+ ? x 0 0 (1?) ? : 0 : -;
+ ? ? ? 0 (10) ? : ? : -;
+ ? ? ? 0 (x0) ? : ? : -;
+ ? ? ? 0 (0x) ? : 0 : -;
+ ? (x1) 0 0 ? 0 : ? : 0;
+ ? (x1) 1 ? 0 0 : ? : 1;
+ ? (x1) 0 0 ? 1 : 0 : 0;
+ ? (x1) 1 ? 0 1 : 1 : 1;
+ ? (x1) ? ? 0 x : ? : -;
+ ? (x1) ? 0 ? x : ? : -;
+ ? (1x) 0 0 ? ? : 0 : -;
+ ? (1x) 1 ? 0 ? : 1 : -;
+ ? (x0) 0 0 ? ? : ? : -;
+ ? (x0) 1 ? 0 ? : ? : -;
+ ? (x0) ? 0 0 x : ? : -;
+ ? (0x) 0 0 ? ? : 0 : -;
+ ? (0x) 1 ? 0 ? : 1 : -;
+ ? (01) 0 0 ? ? : ? : 0;
+ ? (01) 1 ? 0 ? : ? : 1;
+ ? (10) ? 0 ? ? : ? : -;
+ ? (10) ? ? 0 ? : ? : -;
+ ? b * 0 ? ? : ? : -;
+ ? b * ? 0 ? : ? : -;
+ ? ? ? ? ? * : ? : -;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_r_
+`else
+`define _udp_def_altos_latch_r_
+primitive altos_latch_r (q, v, clk, d, r);
+ output q;
+ reg q;
+ input v, clk, d, r;
+
+ table
+ * ? ? ? : ? : x;
+ ? ? ? 1 : ? : 0;
+ ? 0 ? 0 : ? : -;
+ ? 0 ? x : 0 : -;
+ ? 1 0 0 : ? : 0;
+ ? 1 0 x : ? : 0;
+ ? 1 1 0 : ? : 1;
+ ? x 0 0 : 0 : -;
+ ? x 0 x : 0 : -;
+ ? x 1 0 : 1 : -;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_s_
+`else
+`define _udp_def_altos_latch_s_
+primitive altos_latch_s (q, v, clk, d, s);
+ output q;
+ reg q;
+ input v, clk, d, s;
+
+ table
+ * ? ? ? : ? : x;
+ ? ? ? 1 : ? : 1;
+ ? 0 ? 0 : ? : -;
+ ? 0 ? x : 1 : -;
+ ? 1 1 0 : ? : 1;
+ ? 1 1 x : ? : 1;
+ ? 1 0 0 : ? : 0;
+ ? x 1 0 : 1 : -;
+ ? x 1 x : 1 : -;
+ ? x 0 0 : 0 : -;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_0
+`else
+`define _udp_def_altos_latch_sr_0
+primitive altos_latch_sr_0 (q, v, clk, d, s, r);
+ output q;
+ reg q;
+ input v, clk, d, s, r;
+
+ table
+ * ? ? ? ? : ? : x;
+ ? 1 1 ? 0 : ? : 1;
+ ? 1 0 0 ? : ? : 0;
+ ? ? ? 1 0 : ? : 1;
+ ? ? ? ? 1 : ? : 0;
+ ? 0 * ? ? : ? : -;
+ ? 0 ? * 0 : 1 : 1;
+ ? 0 ? 0 * : 0 : 0;
+ ? * 1 ? 0 : 1 : 1;
+ ? * 0 0 ? : 0 : 0;
+ ? ? 1 * 0 : 1 : 1;
+ ? ? 0 0 * : 0 : 0;
+ endtable
+endprimitive
+`endif
+
+`ifdef _udp_def_altos_latch_sr_1
+`else
+`define _udp_def_altos_latch_sr_1
+primitive altos_latch_sr_1 (q, v, clk, d, s, r);
+ output q;
+ reg q;
+ input v, clk, d, s, r;
+
+ table
+ * ? ? ? ? : ? : x;
+ ? 1 1 ? 0 : ? : 1;
+ ? 1 0 0 ? : ? : 0;
+ ? ? ? 1 ? : ? : 1;
+ ? ? ? 0 1 : ? : 0;
+ ? 0 * ? ? : ? : -;
+ ? 0 ? * 0 : 1 : 1;
+ ? 0 ? 0 * : 0 : 0;
+ ? * 1 ? 0 : 1 : 1;
+ ? * 0 0 ? : 0 : 0;
+ ? ? 1 * 0 : 1 : 1;
+ ? ? 0 0 * : 0 : 0;
+ endtable
+endprimitive
+`endif
diff --git a/verilog/sky130_osu_sc.v b/verilog/sky130_osu_sc.v
deleted file mode 100644
index 8be6609..0000000
--- a/verilog/sky130_osu_sc.v
+++ /dev/null
@@ -1,1667 +0,0 @@
-// Verilog for library /import/okita1/tdene/final_final/osugooglelib/char/liberate/VERILOG/sky130_osu_sc.v created by Liberate 19.2.1.215 on Wed Apr 15 19:42:51 CDT 2020 for SDF version 2.1
-
-// type: ADDF
-`timescale 1ns/10ps
-`celldefine
-module ADDFX1 (CO, S, A, B, CI);
- output CO, S;
- input A, B, CI;
-
- // Function
- wire A__bar, B__bar, CI__bar;
- wire int_fwire_0, int_fwire_1, int_fwire_2;
- wire int_fwire_3, int_fwire_4, int_fwire_5;
- wire int_fwire_6;
-
- and (int_fwire_0, B, CI);
- and (int_fwire_1, A, CI);
- and (int_fwire_2, A, B);
- or (CO, int_fwire_2, int_fwire_1, int_fwire_0);
- not (B__bar, B);
- not (A__bar, A);
- and (int_fwire_3, A__bar, B__bar, CI);
- not (CI__bar, CI);
- and (int_fwire_4, A__bar, B, CI__bar);
- and (int_fwire_5, A, B__bar, CI__bar);
- and (int_fwire_6, A, B, CI);
- or (S, int_fwire_6, int_fwire_5, int_fwire_4, int_fwire_3);
-
- // Timing
- specify
- if ((B & ~CI))
- (A => CO) = 0;
- if ((~B & CI))
- (A => CO) = 0;
- ifnone (A => CO) = 0;
- if ((A & ~CI))
- (B => CO) = 0;
- if ((~A & CI))
- (B => CO) = 0;
- ifnone (B => CO) = 0;
- if ((A & ~B))
- (CI => CO) = 0;
- if ((~A & B))
- (CI => CO) = 0;
- ifnone (CI => CO) = 0;
- if ((B & CI))
- (A => S) = 0;
- if ((~B & ~CI))
- (A => S) = 0;
- ifnone (A => S) = 0;
- if ((B & ~CI))
- (A => S) = 0;
- if ((~B & CI))
- (A => S) = 0;
- if ((A & CI))
- (B => S) = 0;
- if ((~A & ~CI))
- (B => S) = 0;
- ifnone (B => S) = 0;
- if ((A & ~CI))
- (B => S) = 0;
- if ((~A & CI))
- (B => S) = 0;
- if ((A & B))
- (CI => S) = 0;
- if ((~A & ~B))
- (CI => S) = 0;
- ifnone (CI => S) = 0;
- if ((A & ~B))
- (CI => S) = 0;
- if ((~A & B))
- (CI => S) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: ADDF
-`timescale 1ns/10ps
-`celldefine
-module ADDFXL (CO, S, A, B, CI);
- output CO, S;
- input A, B, CI;
-
- // Function
- or (CO, B, CI);
- buf (S, 1'b1);
-
- // Timing
- specify
- if ((B & ~CI))
- (posedge A => (CO+:1'b1)) = 0;
- if ((~B & CI))
- (posedge A => (CO+:1'b1)) = 0;
- ifnone (posedge A => (CO+:1'b1)) = 0;
- if ((A & ~CI))
- (B => CO) = 0;
- if ((~A & CI))
- (posedge B => (CO+:1'b1)) = 0;
- if ((~A & ~CI))
- (negedge B => (CO+:1'b0)) = 0;
- ifnone (B => CO) = 0;
- if ((A & ~B))
- (CI => CO) = 0;
- if ((~A & B))
- (posedge CI => (CO+:1'b1)) = 0;
- if ((~A & ~B))
- (negedge CI => (CO+:1'b0)) = 0;
- ifnone (CI => CO) = 0;
- if ((B & CI))
- (posedge A => (S+:1'b1)) = 0;
- if ((~B & ~CI))
- (posedge A => (S+:1'b1)) = 0;
- ifnone (posedge A => (S+:1'b1)) = 0;
- if ((A & CI))
- (posedge B => (S+:1'b1)) = 0;
- if ((~A & ~CI))
- (posedge B => (S+:1'b1)) = 0;
- ifnone (posedge B => (S+:1'b1)) = 0;
- if ((A & B))
- (posedge CI => (S+:1'b1)) = 0;
- if ((~A & ~B))
- (posedge CI => (S+:1'b1)) = 0;
- ifnone (posedge CI => (S+:1'b1)) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: ADDH
-`timescale 1ns/10ps
-`celldefine
-module ADDHX1 (CO, S, A, B);
- output CO, S;
- input A, B;
-
- // Function
- wire A__bar, B__bar;
-
- and (CO, A, B);
- not (B__bar, B);
- not (A__bar, A);
- or (S, A__bar, B__bar);
-
- // Timing
- specify
- (A => CO) = 0;
- (B => CO) = 0;
- ifnone (posedge A => (S+:1'b1)) = 0;
- (A => S) = 0;
- ifnone (posedge B => (S+:1'b1)) = 0;
- (B => S) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: ADDH
-`timescale 1ns/10ps
-`celldefine
-module ADDHXL (CO, S, A, B);
- output CO, S;
- input A, B;
-
- // Function
- wire A__bar, B__bar, int_fwire_0;
- wire int_fwire_1;
-
- and (CO, A, B);
- not (A__bar, A);
- and (int_fwire_0, A__bar, B);
- not (B__bar, B);
- and (int_fwire_1, A, B__bar);
- or (S, int_fwire_1, int_fwire_0);
-
- // Timing
- specify
- (A => CO) = 0;
- (B => CO) = 0;
- if (~B)
- (A => S) = 0;
- if (B)
- (A => S) = 0;
- if (~A)
- (B => S) = 0;
- if (A)
- (B => S) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: AND2
-`timescale 1ns/10ps
-`celldefine
-module AND2X1 (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- and (Y, A, B);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: AND2
-`timescale 1ns/10ps
-`celldefine
-module AND2X2 (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- and (Y, A, B);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: AND2
-`timescale 1ns/10ps
-`celldefine
-module AND2X4 (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- and (Y, A, B);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: AND2
-`timescale 1ns/10ps
-`celldefine
-module AND2X8 (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- and (Y, A, B);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: AND2
-`timescale 1ns/10ps
-`celldefine
-module AND2XL (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- and (Y, A, B);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: AND3
-`timescale 1ns/10ps
-`celldefine
-module AND3XL (Y, A, B, C);
- output Y;
- input A, B, C;
-
- // Function
- wire A__bar, B__bar, C__bar;
-
- not (C__bar, C);
- not (B__bar, B);
- not (A__bar, A);
- or (Y, A__bar, B__bar, C__bar);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- (C => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: ANT
-`timescale 1ns/10ps
-`celldefine
-module ANT (A);
- input A;
- // Timing
- specify
- endspecify
-endmodule
-`endcelldefine
-
-// type: AOI21
-`timescale 1ns/10ps
-`celldefine
-module AOI21XL (Y, A0, A1, B0);
- output Y;
- input A0, A1, B0;
-
- // Function
- wire A0__bar, A1__bar, B0__bar;
- wire int_fwire_0, int_fwire_1;
-
- not (B0__bar, B0);
- not (A1__bar, A1);
- and (int_fwire_0, A1__bar, B0__bar);
- not (A0__bar, A0);
- and (int_fwire_1, A0__bar, B0__bar);
- or (Y, int_fwire_1, int_fwire_0);
-
- // Timing
- specify
- (A0 => Y) = 0;
- (A1 => Y) = 0;
- if ((A0 & ~A1))
- (B0 => Y) = 0;
- if ((~A0 & A1))
- (B0 => Y) = 0;
- if ((~A0 & ~A1))
- (B0 => Y) = 0;
- ifnone (B0 => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: BUF
-`timescale 1ns/10ps
-`celldefine
-module BUFX1 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: BUF
-`timescale 1ns/10ps
-`celldefine
-module BUFX2 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: BUF
-`timescale 1ns/10ps
-`celldefine
-module BUFX4 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: BUF
-`timescale 1ns/10ps
-`celldefine
-module BUFX6 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: BUF
-`timescale 1ns/10ps
-`celldefine
-module BUFX8 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: BUF
-`timescale 1ns/10ps
-`celldefine
-module BUFXL (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: CLKBUF
-`timescale 1ns/10ps
-`celldefine
-module CLKBUFX1 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: CLKINV
-`timescale 1ns/10ps
-`celldefine
-module CLKINVX1 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: CLKINV
-`timescale 1ns/10ps
-`celldefine
-module CLKINVX2 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: CLKINV
-`timescale 1ns/10ps
-`celldefine
-module CLKINVX4 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: DFFN
-`timescale 1ns/10ps
-`celldefine
-module DFFNXL (Q, QN, D, CK);
- output Q, QN;
- input D, CK;
- reg notifier;
- wire delayed_D, delayed_CK;
-
- // Function
- wire int_fwire_clk, int_fwire_IQ, int_fwire_IQN;
- wire xcr_0;
-
- not (int_fwire_clk, delayed_CK);
- altos_dff_err (xcr_0, int_fwire_clk, delayed_D);
- altos_dff (int_fwire_IQ, notifier, int_fwire_clk, delayed_D, xcr_0);
- buf (Q, int_fwire_IQ);
- not (int_fwire_IQN, int_fwire_IQ);
- buf (QN, int_fwire_IQN);
-
- // Timing
- specify
- (negedge CK => (Q+:D)) = 0;
- (negedge CK => (QN-:D)) = 0;
- $setuphold (negedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
- $setuphold (negedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
- $width (posedge CK &&& D, 0, 0, notifier);
- $width (negedge CK &&& D, 0, 0, notifier);
- $width (posedge CK &&& ~D, 0, 0, notifier);
- $width (negedge CK &&& ~D, 0, 0, notifier);
- endspecify
-endmodule
-`endcelldefine
-
-// type: DFFR
-`timescale 1ns/10ps
-`celldefine
-module DFFRXL (Q, QN, D, RN, CK);
- output Q, QN;
- input D, RN, CK;
- reg notifier;
- wire delayed_D, delayed_CK;
-
- // Function
- wire int_fwire_IQ, int_fwire_IQN, int_fwire_r;
- wire xcr_0;
-
- not (int_fwire_r, RN);
- altos_dff_r_err (xcr_0, delayed_CK, delayed_D, int_fwire_r);
- altos_dff_r (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_r, xcr_0);
- buf (Q, int_fwire_IQ);
- not (int_fwire_IQN, int_fwire_IQ);
- buf (QN, int_fwire_IQN);
-
- // Timing
-
- // Additional timing wires
- wire adacond0, adacond1, D__bar;
-
-
- // Additional timing gates
- and (adacond0, D, RN);
- not (D__bar, D);
- and (adacond1, D__bar, RN);
-
- specify
- if (CK)
- (negedge RN => (Q+:1'b0)) = 0;
- if ((~CK & D))
- (negedge RN => (Q+:1'b0)) = 0;
- if ((~CK & ~D))
- (negedge RN => (Q+:1'b0)) = 0;
- ifnone (negedge RN => (Q+:1'b0)) = 0;
- (posedge CK => (Q+:D)) = 0;
- if (CK)
- (negedge RN => (QN-:1'b0)) = 0;
- if ((~CK & D))
- (negedge RN => (QN-:1'b0)) = 0;
- if ((~CK & ~D))
- (negedge RN => (QN-:1'b0)) = 0;
- ifnone (negedge RN => (QN-:1'b0)) = 0;
- (posedge CK => (QN-:D)) = 0;
- $setuphold (posedge CK &&& RN, posedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
- $setuphold (posedge CK &&& RN, negedge D &&& RN, 0, 0, notifier,,, delayed_CK, delayed_D);
- $setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
- $setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
- $recovery (posedge RN &&& D, posedge CK &&& D, 0, notifier);
- $recovery (posedge RN, posedge CK, 0, notifier);
- $hold (posedge CK &&& D, posedge RN &&& D, 0, notifier);
- $hold (posedge CK, posedge RN, 0, notifier);
- $width (negedge RN &&& CK, 0, 0, notifier);
- $width (negedge RN &&& ~CK, 0, 0, notifier);
- $width (posedge CK &&& adacond0, 0, 0, notifier);
- $width (negedge CK &&& adacond0, 0, 0, notifier);
- $width (posedge CK &&& adacond1, 0, 0, notifier);
- $width (negedge CK &&& adacond1, 0, 0, notifier);
- endspecify
-endmodule
-`endcelldefine
-
-// type: DFFS
-`timescale 1ns/10ps
-`celldefine
-module DFFSXL (Q, QN, D, SN, CK);
- output Q, QN;
- input D, SN, CK;
- reg notifier;
- wire delayed_D, delayed_CK;
-
- // Function
- wire int_fwire_IQ, int_fwire_IQN, int_fwire_s;
- wire xcr_0;
-
- not (int_fwire_s, SN);
- altos_dff_s_err (xcr_0, delayed_CK, delayed_D, int_fwire_s);
- altos_dff_s (int_fwire_IQ, notifier, delayed_CK, delayed_D, int_fwire_s, xcr_0);
- buf (Q, int_fwire_IQ);
- not (int_fwire_IQN, int_fwire_IQ);
- buf (QN, int_fwire_IQN);
-
- // Timing
-
- // Additional timing wires
- wire adacond0, adacond1, D__bar;
-
-
- // Additional timing gates
- and (adacond0, D, SN);
- not (D__bar, D);
- and (adacond1, D__bar, SN);
-
- specify
- if (CK)
- (negedge SN => (Q+:1'b1)) = 0;
- if ((~CK & D))
- (negedge SN => (Q+:1'b1)) = 0;
- if ((~CK & ~D))
- (negedge SN => (Q+:1'b1)) = 0;
- ifnone (negedge SN => (Q+:1'b1)) = 0;
- (posedge CK => (Q+:D)) = 0;
- if (CK)
- (negedge SN => (QN-:1'b1)) = 0;
- if ((~CK & D))
- (negedge SN => (QN-:1'b1)) = 0;
- if ((~CK & ~D))
- (negedge SN => (QN-:1'b1)) = 0;
- ifnone (negedge SN => (QN-:1'b1)) = 0;
- (posedge CK => (QN-:D)) = 0;
- $setuphold (posedge CK &&& SN, posedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
- $setuphold (posedge CK &&& SN, negedge D &&& SN, 0, 0, notifier,,, delayed_CK, delayed_D);
- $setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
- $setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
- $recovery (posedge SN &&& ~D, posedge CK &&& ~D, 0, notifier);
- $recovery (posedge SN, posedge CK, 0, notifier);
- $hold (posedge CK &&& ~D, posedge SN &&& ~D, 0, notifier);
- $hold (posedge CK, posedge SN, 0, notifier);
- $width (negedge SN &&& CK, 0, 0, notifier);
- $width (negedge SN &&& ~CK, 0, 0, notifier);
- $width (posedge CK &&& adacond0, 0, 0, notifier);
- $width (negedge CK &&& adacond0, 0, 0, notifier);
- $width (posedge CK &&& adacond1, 0, 0, notifier);
- $width (negedge CK &&& adacond1, 0, 0, notifier);
- endspecify
-endmodule
-`endcelldefine
-
-// type: DFF
-`timescale 1ns/10ps
-`celldefine
-module DFFXL (Q, QN, D, CK);
- output Q, QN;
- input D, CK;
- reg notifier;
- wire delayed_D, delayed_CK;
-
- // Function
- wire delayed_D__bar, int_fwire_0, int_fwire_d;
- wire int_fwire_IQ, int_fwire_IQN, xcr_0;
-
- not (delayed_D__bar, delayed_D);
- and (int_fwire_0, delayed_D__bar, int_fwire_IQ);
- or (int_fwire_d, delayed_D, int_fwire_0);
- altos_dff_err (xcr_0, delayed_CK, int_fwire_d);
- altos_dff (int_fwire_IQ, notifier, delayed_CK, int_fwire_d, xcr_0);
- buf (Q, int_fwire_IQ);
- not (int_fwire_IQN, int_fwire_IQ);
- buf (QN, int_fwire_IQN);
-
- // Timing
- specify
- (posedge CK => (Q+:((D) || (!D && int_fwire_IQ)))) = 0;
- (posedge CK => (QN-:((D) || (!D && int_fwire_IQ)))) = 0;
- $setuphold (posedge CK, posedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
- $setuphold (posedge CK, negedge D, 0, 0, notifier,,, delayed_CK, delayed_D);
- $width (posedge CK &&& D, 0, 0, notifier);
- $width (negedge CK &&& D, 0, 0, notifier);
- endspecify
-endmodule
-`endcelldefine
-
-// type: DLY1
-`timescale 1ns/10ps
-`celldefine
-module DLY1 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: DLY2
-`timescale 1ns/10ps
-`celldefine
-module DLY2 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: DLY3
-`timescale 1ns/10ps
-`celldefine
-module DLY3 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: DLY4
-`timescale 1ns/10ps
-`celldefine
-module DLY4 (Y, A);
- output Y;
- input A;
-
- // Function
- buf (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: INV
-`timescale 1ns/10ps
-`celldefine
-module INVX1 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: INV
-`timescale 1ns/10ps
-`celldefine
-module INVX10 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: INV
-`timescale 1ns/10ps
-`celldefine
-module INVX2 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: INV
-`timescale 1ns/10ps
-`celldefine
-module INVX3 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: INV
-`timescale 1ns/10ps
-`celldefine
-module INVX4 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: INV
-`timescale 1ns/10ps
-`celldefine
-module INVX6 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: INV
-`timescale 1ns/10ps
-`celldefine
-module INVX8 (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: INV
-`timescale 1ns/10ps
-`celldefine
-module INVXL (Y, A);
- output Y;
- input A;
-
- // Function
- not (Y, A);
-
- // Timing
- specify
- (A => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: NAND2
-`timescale 1ns/10ps
-`celldefine
-module NAND2X1 (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- wire A__bar, B__bar;
-
- not (B__bar, B);
- not (A__bar, A);
- or (Y, A__bar, B__bar);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: NAND2
-`timescale 1ns/10ps
-`celldefine
-module NAND2XL (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- wire A__bar, B__bar;
-
- not (B__bar, B);
- not (A__bar, A);
- or (Y, A__bar, B__bar);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: NAND3
-`timescale 1ns/10ps
-`celldefine
-module NAND3X1 (Y, A, B, C);
- output Y;
- input A, B, C;
-
- // Function
- wire A__bar, B__bar, C__bar;
-
- not (C__bar, C);
- not (B__bar, B);
- not (A__bar, A);
- or (Y, A__bar, B__bar, C__bar);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- (C => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: NAND3
-`timescale 1ns/10ps
-`celldefine
-module NAND3XL (Y, A, B, C);
- output Y;
- input A, B, C;
-
- // Function
- wire A__bar, B__bar, C__bar;
-
- not (C__bar, C);
- not (B__bar, B);
- not (A__bar, A);
- or (Y, A__bar, B__bar, C__bar);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- (C => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: NOR2
-`timescale 1ns/10ps
-`celldefine
-module NOR2X1 (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- wire A__bar, B__bar;
-
- not (B__bar, B);
- not (A__bar, A);
- and (Y, A__bar, B__bar);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: NOR2
-`timescale 1ns/10ps
-`celldefine
-module NOR2XL (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- wire A__bar, B__bar;
-
- not (B__bar, B);
- not (A__bar, A);
- and (Y, A__bar, B__bar);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: OAI21
-`timescale 1ns/10ps
-`celldefine
-module OAI21XL (Y, A0, A1, B0);
- output Y;
- input A0, A1, B0;
-
- // Function
- wire A0__bar, A1__bar, B0__bar;
- wire int_fwire_0;
-
- not (B0__bar, B0);
- not (A1__bar, A1);
- not (A0__bar, A0);
- and (int_fwire_0, A0__bar, A1__bar);
- or (Y, int_fwire_0, B0__bar);
-
- // Timing
- specify
- (A0 => Y) = 0;
- (A1 => Y) = 0;
- if ((A0 & A1))
- (B0 => Y) = 0;
- if ((A0 & ~A1))
- (B0 => Y) = 0;
- if ((~A0 & A1))
- (B0 => Y) = 0;
- ifnone (B0 => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: OR2
-`timescale 1ns/10ps
-`celldefine
-module OR2X1 (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- or (Y, A, B);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: OR2
-`timescale 1ns/10ps
-`celldefine
-module OR2X2 (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- buf (Y, 1'b1);
-
- // Timing
- specify
- ifnone (posedge A => (Y+:1'b1)) = 0;
- ifnone (posedge B => (Y+:1'b1)) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: OR2
-`timescale 1ns/10ps
-`celldefine
-module OR2X4 (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- or (Y, A, B);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: OR2
-`timescale 1ns/10ps
-`celldefine
-module OR2XL (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- or (Y, A, B);
-
- // Timing
- specify
- (A => Y) = 0;
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: TBUF
-`timescale 1ns/10ps
-`celldefine
-module TBUFXL (Y, A);
- output Y;
- input A;
-
- // Function
- bufif1 (Y, 1'b1, A);
-
- // Timing
- specify
- (A => Y) = 0;
- (negedge A => (Y:1)) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: TIEHI
-`timescale 1ns/10ps
-`celldefine
-module TIEHI (Y);
- output Y;
-
- // Function
- buf (Y, 1'b1);
-
- // Timing
- specify
- endspecify
-endmodule
-`endcelldefine
-
-// type: TIELO
-`timescale 1ns/10ps
-`celldefine
-module TIELO (Y);
- output Y;
-
- // Function
- buf (Y, 1'b0);
-
- // Timing
- specify
- endspecify
-endmodule
-`endcelldefine
-
-// type: TNBUF
-`timescale 1ns/10ps
-`celldefine
-module TNBUFXL (Y, A);
- output Y;
- input A;
-
- // Function
- bufif0 (Y, 1'b1, A);
-
- // Timing
- specify
- (A => Y) = 0;
- (negedge A => (Y:1)) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: XNOR2
-`timescale 1ns/10ps
-`celldefine
-module XNOR2XL (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- wire A__bar, B__bar, int_fwire_0;
- wire int_fwire_1;
-
- not (B__bar, B);
- not (A__bar, A);
- and (int_fwire_0, A__bar, B__bar);
- and (int_fwire_1, A, B);
- or (Y, int_fwire_1, int_fwire_0);
-
- // Timing
- specify
- if (B)
- (A => Y) = 0;
- if (~B)
- (A => Y) = 0;
- if (A)
- (B => Y) = 0;
- if (~A)
- (B => Y) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-// type: XOR2
-`timescale 1ns/10ps
-`celldefine
-module XOR2XL (Y, A, B);
- output Y;
- input A, B;
-
- // Function
- wire A__bar, int_fwire_enable;
-
- not (A__bar, A);
- and (int_fwire_enable, A__bar, B);
- bufif0 (Y, 1'b1, int_fwire_enable);
-
- // Timing
- specify
- (A => Y) = 0;
- ifnone (posedge A => (Y-:1'b0)) = 0;
- (negedge A => (Y:1)) = 0;
- ifnone (negedge B => (Y+:1'b0)) = 0;
- (B => Y) = 0;
- (posedge B => (Y:1)) = 0;
- endspecify
-endmodule
-`endcelldefine
-
-
-`ifdef _udp_def_altos_latch_
-`else
-`define _udp_def_altos_latch_
-primitive altos_latch (q, v, clk, d);
- output q;
- reg q;
- input v, clk, d;
-
- table
- * ? ? : ? : x;
- ? 1 0 : ? : 0;
- ? 1 1 : ? : 1;
- ? x 0 : 0 : -;
- ? x 1 : 1 : -;
- ? 0 ? : ? : -;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_dff_err_
-`else
-`define _udp_def_altos_dff_err_
-primitive altos_dff_err (q, clk, d);
- output q;
- reg q;
- input clk, d;
-
- table
- (0x) ? : ? : 0;
- (1x) ? : ? : 1;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_dff_
-`else
-`define _udp_def_altos_dff_
-primitive altos_dff (q, v, clk, d, xcr);
- output q;
- reg q;
- input v, clk, d, xcr;
-
- table
- * ? ? ? : ? : x;
- ? (x1) 0 0 : ? : 0;
- ? (x1) 1 0 : ? : 1;
- ? (x1) 0 1 : 0 : 0;
- ? (x1) 1 1 : 1 : 1;
- ? (x1) ? x : ? : -;
- ? (bx) 0 ? : 0 : -;
- ? (bx) 1 ? : 1 : -;
- ? (x0) b ? : ? : -;
- ? (x0) ? x : ? : -;
- ? (01) 0 ? : ? : 0;
- ? (01) 1 ? : ? : 1;
- ? (10) ? ? : ? : -;
- ? b * ? : ? : -;
- ? ? ? * : ? : -;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_dff_r_err_
-`else
-`define _udp_def_altos_dff_r_err_
-primitive altos_dff_r_err (q, clk, d, r);
- output q;
- reg q;
- input clk, d, r;
-
- table
- ? 0 (0x) : ? : -;
- ? 0 (x0) : ? : -;
- (0x) ? 0 : ? : 0;
- (0x) 0 x : ? : 0;
- (1x) ? 0 : ? : 1;
- (1x) 0 x : ? : 1;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_dff_r_
-`else
-`define _udp_def_altos_dff_r_
-primitive altos_dff_r (q, v, clk, d, r, xcr);
- output q;
- reg q;
- input v, clk, d, r, xcr;
-
- table
- * ? ? ? ? : ? : x;
- ? ? ? 1 ? : ? : 0;
- ? b ? (1?) ? : 0 : -;
- ? x 0 (1?) ? : 0 : -;
- ? ? ? (10) ? : ? : -;
- ? ? ? (x0) ? : ? : -;
- ? ? ? (0x) ? : 0 : -;
- ? (x1) 0 ? 0 : ? : 0;
- ? (x1) 1 0 0 : ? : 1;
- ? (x1) 0 ? 1 : 0 : 0;
- ? (x1) 1 0 1 : 1 : 1;
- ? (x1) ? ? x : ? : -;
- ? (bx) 0 ? ? : 0 : -;
- ? (bx) 1 0 ? : 1 : -;
- ? (x0) 0 ? ? : ? : -;
- ? (x0) 1 0 ? : ? : -;
- ? (x0) ? 0 x : ? : -;
- ? (01) 0 ? ? : ? : 0;
- ? (01) 1 0 ? : ? : 1;
- ? (10) ? ? ? : ? : -;
- ? b * ? ? : ? : -;
- ? ? ? ? * : ? : -;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_dff_s_err_
-`else
-`define _udp_def_altos_dff_s_err_
-primitive altos_dff_s_err (q, clk, d, s);
- output q;
- reg q;
- input clk, d, s;
-
- table
- ? 1 (0x) : ? : -;
- ? 1 (x0) : ? : -;
- (0x) ? 0 : ? : 0;
- (0x) 1 x : ? : 0;
- (1x) ? 0 : ? : 1;
- (1x) 1 x : ? : 1;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_dff_s_
-`else
-`define _udp_def_altos_dff_s_
-primitive altos_dff_s (q, v, clk, d, s, xcr);
- output q;
- reg q;
- input v, clk, d, s, xcr;
-
- table
- * ? ? ? ? : ? : x;
- ? ? ? 1 ? : ? : 1;
- ? b ? (1?) ? : 1 : -;
- ? x 1 (1?) ? : 1 : -;
- ? ? ? (10) ? : ? : -;
- ? ? ? (x0) ? : ? : -;
- ? ? ? (0x) ? : 1 : -;
- ? (x1) 0 0 0 : ? : 0;
- ? (x1) 1 ? 0 : ? : 1;
- ? (x1) 1 ? 1 : 1 : 1;
- ? (x1) 0 0 1 : 0 : 0;
- ? (x1) ? ? x : ? : -;
- ? (bx) 1 ? ? : 1 : -;
- ? (bx) 0 0 ? : 0 : -;
- ? (x0) 1 ? ? : ? : -;
- ? (x0) 0 0 ? : ? : -;
- ? (x0) ? 0 x : ? : -;
- ? (01) 1 ? ? : ? : 1;
- ? (01) 0 0 ? : ? : 0;
- ? (10) ? ? ? : ? : -;
- ? b * ? ? : ? : -;
- ? ? ? ? * : ? : -;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_dff_sr_err_
-`else
-`define _udp_def_altos_dff_sr_err_
-primitive altos_dff_sr_err (q, clk, d, s, r);
- output q;
- reg q;
- input clk, d, s, r;
-
- table
- ? 1 (0x) ? : ? : -;
- ? 0 ? (0x) : ? : -;
- ? 0 ? (x0) : ? : -;
- (0x) ? 0 0 : ? : 0;
- (0x) 1 x 0 : ? : 0;
- (0x) 0 0 x : ? : 0;
- (1x) ? 0 0 : ? : 1;
- (1x) 1 x 0 : ? : 1;
- (1x) 0 0 x : ? : 1;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_dff_sr_0
-`else
-`define _udp_def_altos_dff_sr_0
-primitive altos_dff_sr_0 (q, v, clk, d, s, r, xcr);
- output q;
- reg q;
- input v, clk, d, s, r, xcr;
-
- table
- // v, clk, d, s, r : q' : q;
-
- * ? ? ? ? ? : ? : x;
- ? ? ? ? 1 ? : ? : 0;
- ? ? ? 1 0 ? : ? : 1;
- ? b ? (1?) 0 ? : 1 : -;
- ? x 1 (1?) 0 ? : 1 : -;
- ? ? ? (10) 0 ? : ? : -;
- ? ? ? (x0) 0 ? : ? : -;
- ? ? ? (0x) 0 ? : 1 : -;
- ? b ? 0 (1?) ? : 0 : -;
- ? x 0 0 (1?) ? : 0 : -;
- ? ? ? 0 (10) ? : ? : -;
- ? ? ? 0 (x0) ? : ? : -;
- ? ? ? 0 (0x) ? : 0 : -;
- ? (x1) 0 0 ? 0 : ? : 0;
- ? (x1) 1 ? 0 0 : ? : 1;
- ? (x1) 0 0 ? 1 : 0 : 0;
- ? (x1) 1 ? 0 1 : 1 : 1;
- ? (x1) ? ? 0 x : ? : -;
- ? (x1) ? 0 ? x : ? : -;
- ? (1x) 0 0 ? ? : 0 : -;
- ? (1x) 1 ? 0 ? : 1 : -;
- ? (x0) 0 0 ? ? : ? : -;
- ? (x0) 1 ? 0 ? : ? : -;
- ? (x0) ? 0 0 x : ? : -;
- ? (0x) 0 0 ? ? : 0 : -;
- ? (0x) 1 ? 0 ? : 1 : -;
- ? (01) 0 0 ? ? : ? : 0;
- ? (01) 1 ? 0 ? : ? : 1;
- ? (10) ? 0 ? ? : ? : -;
- ? (10) ? ? 0 ? : ? : -;
- ? b * 0 ? ? : ? : -;
- ? b * ? 0 ? : ? : -;
- ? ? ? ? ? * : ? : -;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_dff_sr_1
-`else
-`define _udp_def_altos_dff_sr_1
-primitive altos_dff_sr_1 (q, v, clk, d, s, r, xcr);
- output q;
- reg q;
- input v, clk, d, s, r, xcr;
-
- table
- // v, clk, d, s, r : q' : q;
-
- * ? ? ? ? ? : ? : x;
- ? ? ? 0 1 ? : ? : 0;
- ? ? ? 1 ? ? : ? : 1;
- ? b ? (1?) 0 ? : 1 : -;
- ? x 1 (1?) 0 ? : 1 : -;
- ? ? ? (10) 0 ? : ? : -;
- ? ? ? (x0) 0 ? : ? : -;
- ? ? ? (0x) 0 ? : 1 : -;
- ? b ? 0 (1?) ? : 0 : -;
- ? x 0 0 (1?) ? : 0 : -;
- ? ? ? 0 (10) ? : ? : -;
- ? ? ? 0 (x0) ? : ? : -;
- ? ? ? 0 (0x) ? : 0 : -;
- ? (x1) 0 0 ? 0 : ? : 0;
- ? (x1) 1 ? 0 0 : ? : 1;
- ? (x1) 0 0 ? 1 : 0 : 0;
- ? (x1) 1 ? 0 1 : 1 : 1;
- ? (x1) ? ? 0 x : ? : -;
- ? (x1) ? 0 ? x : ? : -;
- ? (1x) 0 0 ? ? : 0 : -;
- ? (1x) 1 ? 0 ? : 1 : -;
- ? (x0) 0 0 ? ? : ? : -;
- ? (x0) 1 ? 0 ? : ? : -;
- ? (x0) ? 0 0 x : ? : -;
- ? (0x) 0 0 ? ? : 0 : -;
- ? (0x) 1 ? 0 ? : 1 : -;
- ? (01) 0 0 ? ? : ? : 0;
- ? (01) 1 ? 0 ? : ? : 1;
- ? (10) ? 0 ? ? : ? : -;
- ? (10) ? ? 0 ? : ? : -;
- ? b * 0 ? ? : ? : -;
- ? b * ? 0 ? : ? : -;
- ? ? ? ? ? * : ? : -;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_latch_r_
-`else
-`define _udp_def_altos_latch_r_
-primitive altos_latch_r (q, v, clk, d, r);
- output q;
- reg q;
- input v, clk, d, r;
-
- table
- * ? ? ? : ? : x;
- ? ? ? 1 : ? : 0;
- ? 0 ? 0 : ? : -;
- ? 0 ? x : 0 : -;
- ? 1 0 0 : ? : 0;
- ? 1 0 x : ? : 0;
- ? 1 1 0 : ? : 1;
- ? x 0 0 : 0 : -;
- ? x 0 x : 0 : -;
- ? x 1 0 : 1 : -;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_latch_s_
-`else
-`define _udp_def_altos_latch_s_
-primitive altos_latch_s (q, v, clk, d, s);
- output q;
- reg q;
- input v, clk, d, s;
-
- table
- * ? ? ? : ? : x;
- ? ? ? 1 : ? : 1;
- ? 0 ? 0 : ? : -;
- ? 0 ? x : 1 : -;
- ? 1 1 0 : ? : 1;
- ? 1 1 x : ? : 1;
- ? 1 0 0 : ? : 0;
- ? x 1 0 : 1 : -;
- ? x 1 x : 1 : -;
- ? x 0 0 : 0 : -;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_latch_sr_0
-`else
-`define _udp_def_altos_latch_sr_0
-primitive altos_latch_sr_0 (q, v, clk, d, s, r);
- output q;
- reg q;
- input v, clk, d, s, r;
-
- table
- * ? ? ? ? : ? : x;
- ? 1 1 ? 0 : ? : 1;
- ? 1 0 0 ? : ? : 0;
- ? ? ? 1 0 : ? : 1;
- ? ? ? ? 1 : ? : 0;
- ? 0 * ? ? : ? : -;
- ? 0 ? * 0 : 1 : 1;
- ? 0 ? 0 * : 0 : 0;
- ? * 1 ? 0 : 1 : 1;
- ? * 0 0 ? : 0 : 0;
- ? ? 1 * 0 : 1 : 1;
- ? ? 0 0 * : 0 : 0;
- endtable
-endprimitive
-`endif
-
-`ifdef _udp_def_altos_latch_sr_1
-`else
-`define _udp_def_altos_latch_sr_1
-primitive altos_latch_sr_1 (q, v, clk, d, s, r);
- output q;
- reg q;
- input v, clk, d, s, r;
-
- table
- * ? ? ? ? : ? : x;
- ? 1 1 ? 0 : ? : 1;
- ? 1 0 0 ? : ? : 0;
- ? ? ? 1 ? : ? : 1;
- ? ? ? 0 1 : ? : 0;
- ? 0 * ? ? : ? : -;
- ? 0 ? * 0 : 1 : 1;
- ? 0 ? 0 * : 0 : 0;
- ? * 1 ? 0 : 1 : 1;
- ? * 0 0 ? : 0 : 0;
- ? ? 1 * 0 : 1 : 1;
- ? ? 0 0 * : 0 : 0;
- endtable
-endprimitive
-`endif
