blob: cafc275c9f008a4ad0e9a8c1d10c91c95b194c98 [file] [log] [blame]
Kevin Kelleye1014fa2020-05-06 11:00:01 +07001{
2 "description": "2-input AND into all inputs of 3-input OR.",
3 "equation": "X = ((A1 & A2) | (B1 & B2) | (C1 & C2))",
4 "file_prefix": "sky130_fd_sc_ms__a222o",
5 "library": "sky130_fd_sc_ms",
6 "name": "a222o",
7 "parameters": [],
8 "ports": [
9 [
10 "signal",
11 "X",
12 "output",
13 ""
14 ],
15 [
16 "signal",
17 "A1",
18 "input",
19 ""
20 ],
21 [
22 "signal",
23 "A2",
24 "input",
25 ""
26 ],
27 [
28 "signal",
29 "B1",
30 "input",
31 ""
32 ],
33 [
34 "signal",
35 "B2",
36 "input",
37 ""
38 ],
39 [
40 "signal",
41 "C1",
42 "input",
43 ""
44 ],
45 [
46 "signal",
47 "C2",
48 "input",
49 ""
50 ],
51 [
52 "power",
53 "VPWR",
54 "input",
55 "supply1"
56 ],
57 [
58 "power",
59 "VGND",
60 "input",
61 "supply0"
62 ],
63 [
64 "power",
65 "VPB",
66 "input",
67 "supply1"
68 ],
69 [
70 "power",
71 "VNB",
72 "input",
73 "supply0"
74 ]
75 ],
76 "type": "cell",
77 "verilog_name": "sky130_fd_sc_ms__a222o"
78}