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| "cell_footprint": "dlxtp", |
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| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "latch IQ,IQ_N": { |
| "data_in": "D", |
| "enable": "GATE" |
| }, |
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| }, |
| { |
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| { |
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| ], |
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| "voltage_name": "VGND" |
| }, |
| "pg_pin VNB": { |
| "pg_type": "primary_ground", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin VPB": { |
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| "voltage_name": "VPB" |
| }, |
| "pg_pin VPWR": { |
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| "voltage_name": "VPWR" |
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| }, |
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| }, |
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| }, |
| "pin Q": { |
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| "function": "IQ", |
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