| { | |
| "area": 22.3776, | |
| "cell_footprint": "dlrtp", | |
| "cell_leakage_power": 0.0, | |
| "latch IQ,IQ_N": { | |
| "clear": "!RESET_B", | |
| "data_in": "D", | |
| "enable": "GATE" | |
| }, | |
| "pg_pin VGND": { | |
| "pg_type": "primary_ground", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin VNB": { | |
| "pg_type": "primary_ground", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin VPB": { | |
| "pg_type": "primary_power", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin VPWR": { | |
| "pg_type": "primary_power", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin D": { | |
| "capacitance": 0.00247, | |
| "clock": "false", | |
| "direction": "input", | |
| "internal_power": { | |
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| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
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| { | |
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| { | |
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| "rise_constraint sethold_template_rise10x10": { | |
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| }, | |
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| } | |
| ] | |
| }, | |
| "pin GATE": { | |
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| "clock": "true", | |
| "direction": "input", | |
| "internal_power": { | |
| "fall_power hidden_pwr_template13": { | |
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| "rise_power hidden_pwr_template13": { | |
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| } | |
| }, | |
| "max_transition": 1.0, | |
| "min_pulse_width_high": 0.07233, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
| }, | |
| "pin Q": { | |
| "direction": "output", | |
| "function": "IQ", | |
| "internal_power": [ | |
| { | |
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