| { |
| "area": 28.7712, |
| "cell_footprint": "sky130_fd_sc_ms__dlclkp", |
| "cell_leakage_power": 0.0, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.0126, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
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| "related_power_pin": "VPWR" |
| }, |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
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| }, |
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| }, |
| { |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
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| 0.07737, |
| 0.18352, |
| 0.23631, |
| 0.31583, |
| 0.43702, |
| 0.62034, |
| 0.89479, |
| 1.31306, |
| 1.9336, |
| 2.862, |
| 4.2605 |
| ], |
| [ |
| 0.07738, |
| 0.18342, |
| 0.23659, |
| 0.31592, |
| 0.43695, |
| 0.61952, |
| 0.89471, |
| 1.31296, |
| 1.9305, |
| 2.8671, |
| 4.2663 |
| ], |
| [ |
| 0.07733, |
| 0.18362, |
| 0.23662, |
| 0.31595, |
| 0.43708, |
| 0.62041, |
| 0.89667, |
| 1.3094, |
| 1.9349, |
| 2.8565, |
| 4.2561 |
| ], |
| [ |
| 0.07724, |
| 0.18358, |
| 0.23636, |
| 0.31596, |
| 0.43716, |
| 0.6198, |
| 0.8954, |
| 1.3129, |
| 1.934, |
| 2.8675, |
| 4.2655 |
| ], |
| [ |
| 0.0775, |
| 0.1833, |
| 0.2364, |
| 0.3159, |
| 0.4369, |
| 0.6198, |
| 0.8947, |
| 1.3085, |
| 1.9345, |
| 2.86, |
| 4.2637 |
| ], |
| [ |
| 0.0801, |
| 0.185, |
| 0.2378, |
| 0.3166, |
| 0.4379, |
| 0.6204, |
| 0.8957, |
| 1.309, |
| 1.9335, |
| 2.8565, |
| 4.2579 |
| ], |
| [ |
| 0.0845, |
| 0.1892, |
| 0.2408, |
| 0.3195, |
| 0.4399, |
| 0.6221, |
| 0.8977, |
| 1.3093, |
| 1.9353, |
| 2.8565, |
| 4.2581 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
