| { |
| "area": 28.7712, |
| "cell_footprint": "sky130_fd_sc_ms__dlclkp", |
| "cell_leakage_power": 22.31278, |
| "clock_gating_integrated_cell": "latch_posedge", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 19.1727398, |
| "when": "!GATE&CLK" |
| }, |
| { |
| "value": 20.2554524, |
| "when": "GATE&!CLK" |
| }, |
| { |
| "value": 18.6659719, |
| "when": "GATE&CLK" |
| }, |
| { |
| "value": 22.3127845, |
| "when": "!GATE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.01283, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
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| ], |
| "values": [ |
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| 0.046348, |
| 0.0554772, |
| 0.0691759, |
| 0.0897316 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| ], |
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| 0.0323997, |
| 0.0461992, |
| 0.0669069 |
| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "min_pulse_width_low": 0.09577, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR" |
| }, |
| "pin,GATE": { |
| "capacitance": 0.00265, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "internal_power": { |
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| 0.01735, |
| 0.02602, |
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| 0.44449, |
| 0.6667, |
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| ], |
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| 0.0367741, |
| 0.0390455, |
| 0.0438137, |
| 0.0509713, |
| 0.061713, |
| 0.0778327 |
| ] |
| }, |
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| 0.44449, |
| 0.6667, |
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| ], |
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| 0.0259673, |
| 0.0307877, |
| 0.0380238, |
| 0.0488835, |
| 0.0651807 |
| ] |
| } |
| }, |
| "max_transition": 1.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "timing": [ |
| { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
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| [ |
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| 0.2812, |
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| [ |
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| 0.2314, |
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| 0.35152, |
| 0.38667 |
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| [ |
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| 0.30171, |
| 0.29878, |
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| [ |
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| 0.48042, |
| 0.51558 |
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| [ |
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| 0.42769, |
| 0.42769, |
| 0.42183, |
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| 0.45113, |
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| 0.53902, |
| 0.57417 |
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| [ |
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| 0.50972, |
| 0.53316, |
| 0.56831, |
| 0.59761, |
| 0.63277 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
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| 0.05562, |
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| 0.07906, |
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| 0.2021, |
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| [ |
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| [ |
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| [ |
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| 0.21089, |
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| [ |
| 0.00581, |
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| 0.0937, |
| 0.13472, |
| 0.17866, |
| 0.22261 |
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| [ |
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| [ |
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| 0.1523 |
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| [ |
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| 0.02339, |
| 0.07027, |
| 0.11421 |
| ] |
| ] |
| }, |
| "timing_type": "setup_rising" |
| }, |
| { |
| "fall_constraint,sethold_template_fall10x10": { |
| "index_1": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| -0.49223, |
| -0.52153, |
| -0.55083 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,sethold_template_rise10x10": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
| "index_2": [ |
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| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
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| ], |
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| [ |
| 0.01167, |
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| 0.01167, |
| 0.00581, |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| 0.00288, |
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| ] |
| }, |
| "timing_type": "hold_rising" |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x13": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
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| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1, |
| 1.5 |
| ], |
| "index_2": [ |
| 0, |
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| 0.37674, |
| 0.56511, |
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| [ |
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| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_transition,delay_template13x13": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
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| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
| "index_2": [ |
| 0.0, |
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| "values": [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| 0.4541, |
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| 1.001, |
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| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
