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| "cell_footprint": "sky130_fd_sc_ms__dlclkp", |
| "cell_leakage_power": 0.0, |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
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| "physical_connection": "device_layer", |
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| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
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| "clock": "true", |
| "clock_gate_clock_pin": "true", |
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| }, |
| "pin,GCLK": { |
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| 0.45251, |
| 0.67285, |
| 1.00404, |
| 1.50222 |
| ], |
| [ |
| 0.01923, |
| 0.05699, |
| 0.07475, |
| 0.10187, |
| 0.14395, |
| 0.20797, |
| 0.30538, |
| 0.4534, |
| 0.6726, |
| 1.00452, |
| 1.5004 |
| ], |
| [ |
| 0.0209, |
| 0.05909, |
| 0.07662, |
| 0.10348, |
| 0.14492, |
| 0.20891, |
| 0.30578, |
| 0.45196, |
| 0.6729, |
| 1.00379, |
| 1.50092 |
| ], |
| [ |
| 0.02322, |
| 0.06195, |
| 0.0792, |
| 0.1056, |
| 0.14642, |
| 0.2099, |
| 0.30667, |
| 0.45267, |
| 0.67272, |
| 1.00617, |
| 1.50027 |
| ], |
| [ |
| 0.02613, |
| 0.06625, |
| 0.08298, |
| 0.10895, |
| 0.14907, |
| 0.21164, |
| 0.30781, |
| 0.45365, |
| 0.67542, |
| 1.00314, |
| 1.5007 |
| ], |
| [ |
| 0.02997, |
| 0.07225, |
| 0.08904, |
| 0.11422, |
| 0.15361, |
| 0.2152, |
| 0.3098, |
| 0.4552, |
| 0.6746, |
| 1.006, |
| 1.4998 |
| ], |
| [ |
| 0.0351, |
| 0.0803, |
| 0.0971, |
| 0.1224, |
| 0.1605, |
| 0.2212, |
| 0.3152, |
| 0.4593, |
| 0.6782, |
| 1.0066, |
| 1.5008 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
