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| "cell_footprint": "sky130_fd_sc_ms__dlclkp", |
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| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
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| "pg_pin,VPB": { |
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| "voltage_name": "VPWR" |
| }, |
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| "clock_gate_clock_pin": "true", |
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| }, |
| "pin,GCLK": { |
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| 0.07036, |
| 0.098, |
| 0.13963, |
| 0.20316, |
| 0.29816, |
| 0.44072, |
| 0.65615, |
| 0.97665, |
| 1.45916, |
| 2.18456 |
| ], |
| [ |
| 0.01789, |
| 0.07084, |
| 0.09854, |
| 0.14011, |
| 0.20306, |
| 0.29827, |
| 0.44065, |
| 0.65514, |
| 0.9771, |
| 1.45957, |
| 2.18218 |
| ], |
| [ |
| 0.01983, |
| 0.0715, |
| 0.09883, |
| 0.14056, |
| 0.20342, |
| 0.29853, |
| 0.44083, |
| 0.65588, |
| 0.97781, |
| 1.45988, |
| 2.18471 |
| ], |
| [ |
| 0.02271, |
| 0.07251, |
| 0.09952, |
| 0.14082, |
| 0.20373, |
| 0.29886, |
| 0.44143, |
| 0.65649, |
| 0.98042, |
| 1.46097, |
| 2.1862 |
| ], |
| [ |
| 0.02671, |
| 0.07454, |
| 0.10086, |
| 0.14151, |
| 0.20412, |
| 0.29891, |
| 0.44139, |
| 0.65587, |
| 0.97922, |
| 1.463, |
| 2.1873 |
| ], |
| [ |
| 0.0321, |
| 0.0782, |
| 0.10333, |
| 0.14296, |
| 0.20484, |
| 0.2994, |
| 0.4418, |
| 0.6559, |
| 0.9766, |
| 1.4612, |
| 2.1825 |
| ], |
| [ |
| 0.0392, |
| 0.0847, |
| 0.1082, |
| 0.1461, |
| 0.2065, |
| 0.3002, |
| 0.4425, |
| 0.6568, |
| 0.9778, |
| 1.4595, |
| 2.1824 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
