| { | |
| "area": 17.5824, | |
| "cell_footprint": "a2bb2oi", | |
| "cell_leakage_power": 0.0, | |
| "pg_pin VGND": { | |
| "pg_type": "primary_ground", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin VNB": { | |
| "pg_type": "primary_ground", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin VPB": { | |
| "pg_type": "primary_power", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin VPWR": { | |
| "pg_type": "primary_power", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin A1_N": { | |
| "capacitance": 0.00284, | |
| "clock": "false", | |
| "direction": "input", | |
| "internal_power": { | |
| "fall_power hidden_pwr_template13": { | |
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| 0.29634, | |
| 0.44449, | |
| 0.6667, | |
| 1.0, | |
| 1.5 | |
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| 0.08904, | |
| 0.12004 | |
| ] | |
| }, | |
| "rise_power hidden_pwr_template13": { | |
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| ] | |
| } | |
| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
| }, | |
| "pin A2_N": { | |
| "capacitance": 0.00293, | |
| "clock": "false", | |
| "direction": "input", | |
| "internal_power": { | |
| "fall_power hidden_pwr_template13": { | |
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| 0.13172, | |
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| 0.44449, | |
| 0.6667, | |
| 1.0, | |
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| 0.02973, | |
| 0.0348, | |
| 0.04615, | |
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| 0.11571 | |
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| "rise_power hidden_pwr_template13": { | |
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| 0.44449, | |
| 0.6667, | |
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| 0.01089, | |
| 0.01095, | |
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| 0.06338, | |
| 0.09423 | |
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| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
| }, | |
| "pin B1": { | |
| "capacitance": 0.00583, | |
| "clock": "false", | |
| "direction": "input", | |
| "internal_power": { | |
| "fall_power hidden_pwr_template13": { | |
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| 0.29634, | |
| 0.44449, | |
| 0.6667, | |
| 1.0, | |
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| ], | |
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| 0.0261, | |
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| 0.02923, | |
| 0.0322, | |
| 0.0366, | |
| 0.04331, | |
| 0.05761, | |
| 0.07358, | |
| 0.10497, | |
| 0.14349 | |
| ] | |
| }, | |
| "rise_power hidden_pwr_template13": { | |
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| 0.44449, | |
| 0.6667, | |
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| 0.07231, | |
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| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
| }, | |
| "pin B2": { | |
| "capacitance": 0.0059, | |
| "clock": "false", | |
| "direction": "input", | |
| "internal_power": { | |
| "fall_power hidden_pwr_template13": { | |
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| 0.29634, | |
| 0.44449, | |
| 0.6667, | |
| 1.0, | |
| 1.5 | |
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| "values": [ | |
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| 0.02863, | |
| 0.03289, | |
| 0.03943, | |
| 0.05324, | |
| 0.06898, | |
| 0.09967, | |
| 0.13769 | |
| ] | |
| }, | |
| "rise_power hidden_pwr_template13": { | |
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| 0.29634, | |
| 0.44449, | |
| 0.6667, | |
| 1.0, | |
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| ], | |
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| 0.01547, | |
| 0.02043, | |
| 0.03203, | |
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| 0.07585, | |
| 0.11359 | |
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| } | |
| }, | |
| "max_transition": 1.0, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR" | |
| }, | |
| "pin Y": { | |
| "direction": "output", | |
| "function": "(A1_N&!B1) | (A1_N&!B2) | (A2_N&!B1) | (A2_N&!B2)", | |
| "internal_power": [ | |
| { | |
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| [ | |
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| [ | |
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| ] | |
| }, | |
| "related_pin": "A1_N", | |
| "rise_power pwr_template13x7": { | |
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| [ | |
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| ] | |
| }, | |
| "when": "(!A2_N&!B1) | (!A2_N&!B2)" | |
| }, | |
| { | |
| "fall_power pwr_template13x7": { | |
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| [ | |
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| [ | |
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| [ | |
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| ] | |
| }, | |
| "related_pin": "A2_N", | |
| "rise_power pwr_template13x7": { | |
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