commit | c3d24b3b50d46c552c712cc770f48ffbbc0bd07f | [log] [tgz] |
---|---|---|
author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
tree | 8791f1a6aa069bf1d7189773f5fa5772147c8903 | |
parent | ab46bcad7c521f54ddb18c3546559bb1d6cc4b38 [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>