| commit | d8c2717829bd09cbf64eec3778dd90fc2a2fafcd | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
| tree | a28dcdb930a04e6beffc3634bb67e6b5c7d6c543 | |
| parent | 8530db93614fd4feda9e46aef13d5427b9e56a4d [diff] |
verilog: Fixing ordering of ports in primitives. Verilog requires the first signal in a primitive's pin list must be the output. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>