commit | 8530db93614fd4feda9e46aef13d5427b9e56a4d | [log] [tgz] |
---|---|---|
author | Tim 'mithro' Ansell <me@mith.ro> | Fri Oct 02 10:01:02 2020 -0700 |
committer | Tim 'mithro' Ansell <tansell@google.com> | Fri Oct 02 10:01:02 2020 -0700 |
tree | 42ff6cf40d8277e9ff080834ed7acc0c3fe4f9a5 | |
parent | 9fad091054f7e0d9ca01b6925c912d29e144f81a [diff] |
verilog: Fixing usage of cell reserved word. `cell` is a Verilog reserved word. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>