)]}'
{
  "commit": "d8c2717829bd09cbf64eec3778dd90fc2a2fafcd",
  "tree": "a28dcdb930a04e6beffc3634bb67e6b5c7d6c543",
  "parents": [
    "8530db93614fd4feda9e46aef13d5427b9e56a4d"
  ],
  "author": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "me@mith.ro",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "committer": {
    "name": "Tim \u0027mithro\u0027 Ansell",
    "email": "tansell@google.com",
    "time": "Fri Oct 02 10:01:02 2020 -0700"
  },
  "message": "verilog: Fixing ordering of ports in primitives.\n\nVerilog requires the first signal in a primitive\u0027s pin list must be the output.\n\nSigned-off-by: Tim \u0027mithro\u0027 Ansell \u003ctansell@google.com\u003e\n",
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