{ | |
"area": 36.7632, | |
"cell_footprint": "sky130_fd_sc_ls__sdfxtp", | |
"cell_leakage_power": 0.006973068, | |
"driver_waveform_fall": "ramp", | |
"driver_waveform_rise": "ramp", | |
"ff,IQ,IQ_N": { | |
"clocked_on": "CLK", | |
"next_state": "(D&!SCE) | (SCD&SCE)" | |
}, | |
"leakage_power": [ | |
{ | |
"value": 0.0094687, | |
"when": "D&!SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 0.0071467, | |
"when": "!D&!SCD&SCE&CLK" | |
}, | |
{ | |
"value": 0.0051162, | |
"when": "!D&SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 0.0062256, | |
"when": "!D&!SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 0.0031026, | |
"when": "!D&!SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 0.0053199, | |
"when": "D&!SCD&SCE&CLK" | |
}, | |
{ | |
"value": 0.007411, | |
"when": "D&SCD&!SCE&CLK" | |
}, | |
{ | |
"value": 0.0075116, | |
"when": "D&!SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 0.0072917, | |
"when": "!D&SCD&SCE&CLK" | |
}, | |
{ | |
"value": 0.0083678, | |
"when": "!D&!SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 0.009469, | |
"when": "D&SCD&SCE&CLK" | |
}, | |
{ | |
"value": 0.0084429, | |
"when": "D&!SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 0.0063373, | |
"when": "!D&SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 0.0075114, | |
"when": "D&SCD&!SCE&!CLK" | |
}, | |
{ | |
"value": 0.0053346, | |
"when": "!D&SCD&SCE&!CLK" | |
}, | |
{ | |
"value": 0.0075119, | |
"when": "D&SCD&SCE&!CLK" | |
} | |
], | |
"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,CLK": { | |
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"clock": "true", | |
"direction": "input", | |
"fall_capacitance": 0.002447, | |
"internal_power": { | |
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"max_transition": 1.5, | |
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"min_pulse_width_low": 0.479587, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.002787 | |
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"pin,D": { | |
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"clock": "false", | |
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"max_transition": 1.5, | |
"nextstate_type": "data", | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"rise_capacitance": 0.001856, | |
"timing": [ | |
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"related_pin": "CLK", | |
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[ | |
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}, | |
"sim_opt": "runlvl=5 accurate=1", | |
"timing_type": "setup_rising", | |
"violation_delay_degrade_pct": 10 | |
}, | |
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