| { |
| "area": 36.7632, |
| "cell_footprint": "sky130_fd_sc_ls__sdfxtp", |
| "cell_leakage_power": 305.0336, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&!SCE) | (SCD&SCE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 371.3375065, |
| "when": "D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 309.8285788, |
| "when": "!D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 269.3506929, |
| "when": "!D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 283.694618, |
| "when": "!D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 262.5087063, |
| "when": "!D&!SCD&!SCE&CLK" |
| }, |
| { |
| "value": 316.2620033, |
| "when": "D&!SCD&SCE&CLK" |
| }, |
| { |
| "value": 236.669166, |
| "when": "D&SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 300.1430855, |
| "when": "!D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 277.7001669, |
| "when": "D&SCD&SCE&!CLK" |
| }, |
| { |
| "value": 238.2563196, |
| "when": "D&SCD&!SCE&CLK" |
| }, |
| { |
| "value": 266.5770751, |
| "when": "D&!SCD&!SCE&!CLK" |
| }, |
| { |
| "value": 404.9341555, |
| "when": "!D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 331.8421307, |
| "when": "!D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 382.5054762, |
| "when": "D&SCD&SCE&CLK" |
| }, |
| { |
| "value": 337.5416782, |
| "when": "D&!SCD&SCE&!CLK" |
| }, |
| { |
| "value": 291.3860726, |
| "when": "!D&SCD&!SCE&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
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| "capacitance": 0.002864, |
| "clock": "true", |
| "direction": "input", |
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| "internal_power": { |
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| 0.01735, |
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| 0.13172, |
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| 0.6667, |
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| 1.5 |
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| 0.0679203, |
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| }, |
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| }, |
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| "min_pulse_width_low": 0.155526, |
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| "related_power_pin": "VPWR", |
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| }, |
| "pin,D": { |
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| "clock": "false", |
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| "internal_power": { |
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| }, |
| "max_transition": 1.5, |
| "nextstate_type": "data", |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00207, |
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| 0.351528, |
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| ] |
| }, |
| "related_pin": "CLK", |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| 0.03125, |
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| 0.25, |
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| 0.75, |
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| }, |
| "related_pin": "CLK", |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
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