| { | |
| "area": 52.7472, | |
| "cell_footprint": "sky130_fd_sc_ls__sdfstp", | |
| "cell_leakage_power": 389.5671, | |
| "driver_waveform_fall": "ramp", | |
| "driver_waveform_rise": "ramp", | |
| "ff,IQ,IQ_N": { | |
| "clocked_on": "CLK", | |
| "next_state": "(D&!SCE) | (SCD&SCE)", | |
| "preset": "!SET_B" | |
| }, | |
| "leakage_power": [ | |
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| { | |
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| "when": "!D&!SCD&SCE&SET_B&CLK" | |
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| { | |
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| "when": "!D&SCD&!SCE&SET_B&CLK" | |
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| { | |
| "value": 396.2238111, | |
| "when": "!D&!SCD&!SCE&SET_B&!CLK" | |
| }, | |
| { | |
| "value": 356.9786031, | |
| "when": "!D&!SCD&!SCE&!SET_B&CLK" | |
| }, | |
| { | |
| "value": 363.0257766, | |
| "when": "!D&!SCD&!SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 418.5396278, | |
| "when": "D&!SCD&SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 328.066875, | |
| "when": "D&SCD&!SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 334.7846871, | |
| "when": "D&!SCD&!SCE&SET_B&!CLK" | |
| }, | |
| { | |
| "value": 355.4926025, | |
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| }, | |
| { | |
| "value": 623.8627179, | |
| "when": "!D&SCD&SCE&SET_B&CLK" | |
| }, | |
| { | |
| "value": 301.3184369, | |
| "when": "D&SCD&!SCE&SET_B&!CLK" | |
| }, | |
| { | |
| "value": 322.0347367, | |
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| }, | |
| { | |
| "value": 376.1947767, | |
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| }, | |
| { | |
| "value": 396.9043689, | |
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| }, | |
| { | |
| "value": 352.3507246, | |
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| }, | |
| { | |
| "value": 373.0667686, | |
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| }, | |
| { | |
| "value": 278.373534, | |
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| }, | |
| { | |
| "value": 446.1487038, | |
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| }, | |
| { | |
| "value": 406.937005, | |
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| }, | |
| { | |
| "value": 600.0354915, | |
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| }, | |
| { | |
| "value": 451.7466436, | |
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| { | |
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| { | |
| "value": 403.3889525, | |
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| }, | |
| { | |
| "value": 364.0869295, | |
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| }, | |
| { | |
| "value": 285.5187802, | |
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| }, | |
| { | |
| "value": 328.3082037, | |
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| }, | |
| { | |
| "value": 364.4879598, | |
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| }, | |
| { | |
| "value": 323.0755965, | |
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| { | |
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| { | |
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| { | |
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| ], | |
| "pg_pin,VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin,VNB": { | |
| "pg_type": "nwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
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| "pg_pin,VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
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| "clock": "true", | |
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| }, | |
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| "related_power_pin": "VPWR", | |
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| "clock": "false", | |
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| "nextstate_type": "data", | |
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| "related_pin": "CLK", | |
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| }, | |
| "sim_opt": "runlvl=5 accurate=1", | |
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