| { | |
| "area": 47.952, | |
| "cell_footprint": "sky130_fd_sc_ls__sdfrtp", | |
| "cell_leakage_power": 50.12826, | |
| "driver_waveform_fall": "ramp", | |
| "driver_waveform_rise": "ramp", | |
| "ff,IQ,IQ_N": { | |
| "clear": "!RESET_B", | |
| "clocked_on": "CLK", | |
| "next_state": "(D&!SCE) | (SCD&SCE)" | |
| }, | |
| "leakage_power": [ | |
| { | |
| "value": 47.4017092, | |
| "when": "D&!SCD&!SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 36.8042343, | |
| "when": "!D&!SCD&SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 34.1330555, | |
| "when": "!D&SCD&!SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 33.5134622, | |
| "when": "!D&!SCD&!SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 29.4930604, | |
| "when": "!D&!SCD&!SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 40.178616, | |
| "when": "!D&!SCD&!SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 44.9027198, | |
| "when": "D&!SCD&SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 40.0366069, | |
| "when": "D&SCD&!SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 41.2249115, | |
| "when": "D&!SCD&!SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 30.2439211, | |
| "when": "D&!SCD&!SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 50.1282571, | |
| "when": "!D&SCD&SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 37.4879896, | |
| "when": "!D&!SCD&SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 33.7636337, | |
| "when": "!D&!SCD&SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 48.7322609, | |
| "when": "D&SCD&SCE&RESET_B&CLK" | |
| }, | |
| { | |
| "value": 38.2385359, | |
| "when": "D&!SCD&SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 33.775045, | |
| "when": "D&!SCD&SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 34.8177061, | |
| "when": "!D&SCD&!SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 29.4997822, | |
| "when": "!D&SCD&!SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 38.9508514, | |
| "when": "D&SCD&!SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 30.2493746, | |
| "when": "D&SCD&!SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 43.9511396, | |
| "when": "!D&SCD&SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 34.5163542, | |
| "when": "!D&SCD&SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 42.554845, | |
| "when": "D&SCD&SCE&RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 34.522099, | |
| "when": "D&SCD&SCE&!RESET_B&CLK" | |
| }, | |
| { | |
| "value": 31.1500798, | |
| "when": "!D&!SCD&!SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 31.1568975, | |
| "when": "!D&SCD&!SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 35.4206264, | |
| "when": "!D&!SCD&SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 36.173347, | |
| "when": "!D&SCD&SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 31.9010347, | |
| "when": "D&!SCD&!SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 31.9063247, | |
| "when": "D&SCD&!SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 35.432258, | |
| "when": "D&!SCD&SCE&!RESET_B&!CLK" | |
| }, | |
| { | |
| "value": 36.1795252, | |
| "when": "D&SCD&SCE&!RESET_B&!CLK" | |
| } | |
| ], | |
| "pg_pin,VGND": { | |
| "pg_type": "primary_ground", | |
| "related_bias_pin": "VPB", | |
| "voltage_name": "VGND" | |
| }, | |
| "pg_pin,VNB": { | |
| "pg_type": "nwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VNB" | |
| }, | |
| "pg_pin,VPB": { | |
| "pg_type": "pwell", | |
| "physical_connection": "device_layer", | |
| "voltage_name": "VPB" | |
| }, | |
| "pg_pin,VPWR": { | |
| "pg_type": "primary_power", | |
| "related_bias_pin": "VNB", | |
| "voltage_name": "VPWR" | |
| }, | |
| "pin,CLK": { | |
| "capacitance": 0.002955, | |
| "clock": "true", | |
| "direction": "input", | |
| "fall_capacitance": 0.002866, | |
| "internal_power": { | |
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| "rise_power,hidden_pwr_template13": { | |
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| 0.047118, | |
| 0.0601594 | |
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| } | |
| }, | |
| "max_transition": 1.0, | |
| "min_pulse_width_high": 0.098404, | |
| "min_pulse_width_low": 0.162117, | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.003044 | |
| }, | |
| "pin,D": { | |
| "capacitance": 0.001946, | |
| "clock": "false", | |
| "direction": "input", | |
| "fall_capacitance": 0.001891, | |
| "internal_power": { | |
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| 0.0259529 | |
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| }, | |
| "rise_power,hidden_pwr_template13": { | |
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| } | |
| }, | |
| "max_transition": 1.0, | |
| "nextstate_type": "data", | |
| "related_ground_pin": "VGND", | |
| "related_power_pin": "VPWR", | |
| "rise_capacitance": 0.002001, | |
| "timing": [ | |
| { | |
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| }, | |
| "related_pin": "CLK", | |
| "rise_constraint,vio_10_10_1": { | |
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| }, | |
| "sim_opt": "runlvl=5 accurate=1", | |
| "timing_type": "setup_rising", | |
| "violation_delay_degrade_pct": 10 | |
| }, | |
| { | |
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