{ | |
"area": 30.3696, | |
"cell_footprint": "sky130_fd_sc_ls__fa", | |
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"pg_pin,VGND": { | |
"pg_type": "primary_ground", | |
"related_bias_pin": "VPB", | |
"voltage_name": "VGND" | |
}, | |
"pg_pin,VNB": { | |
"pg_type": "nwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VNB" | |
}, | |
"pg_pin,VPB": { | |
"pg_type": "pwell", | |
"physical_connection": "device_layer", | |
"voltage_name": "VPB" | |
}, | |
"pg_pin,VPWR": { | |
"pg_type": "primary_power", | |
"related_bias_pin": "VNB", | |
"voltage_name": "VPWR" | |
}, | |
"pin,A": { | |
"capacitance": 0.01193, | |
"clock": "false", | |
"direction": "input", | |
"max_transition": 1.0, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR" | |
}, | |
"pin,B": { | |
"capacitance": 0.01073, | |
"clock": "false", | |
"direction": "input", | |
"max_transition": 1.0, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR" | |
}, | |
"pin,CIN": { | |
"capacitance": 0.00798, | |
"clock": "false", | |
"direction": "input", | |
"max_transition": 1.0, | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR" | |
}, | |
"pin,COUT": { | |
"direction": "output", | |
"function": "(A&B) | (A&CIN) | (B&CIN)", | |
"internal_power": [ | |
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[ | |
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[ | |
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}, | |
"when": "(B&!CIN) | (!B&CIN)" | |
}, | |
{ | |
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[ | |
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[ | |
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[ | |
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"when": "(A&!CIN) | (!A&CIN)" | |
}, | |
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"when": "(A&!B) | (!A&B)" | |
} | |
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"max_capacitance": 0.12045, | |
"power_down_function": "(!VPWR + VGND)", | |
"related_ground_pin": "VGND", | |
"related_power_pin": "VPWR", | |
"timing": [ | |
{ | |
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