| { |
| "area": 22.3776, |
| "cell_footprint": "sky130_fd_sc_ls__dlclkp", |
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| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
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| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
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| "physical_connection": "device_layer", |
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| }, |
| "pg_pin,VPB": { |
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| "voltage_name": "VPWR" |
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| "clock_gate_clock_pin": "true", |
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| } |
| ] |
| }, |
| "pin,GCLK": { |
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| "direction": "output", |
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| 1.5693694 |
| ], |
| [ |
| 0.1146948, |
| 0.2246304, |
| 0.2784822, |
| 0.366668, |
| 0.5064921, |
| 0.7261315, |
| 1.0623736, |
| 1.5747501 |
| ] |
| ] |
| }, |
| "timing_sense": "positive_unate" |
| } |
| }, |
| "pin,M0": { |
| "direction": "internal", |
| "internal_node": "M0", |
| "related_ground_pin": "VNB", |
| "related_power_pin": "VPWR" |
| }, |
| "statetable,CLK GATE,M0": { |
| "table": [ |
| "L L : - : L", |
| "L H : - : H", |
| "H - : - : N" |
| ] |
| } |
| } |
