| { |
| "area": 31.968, |
| "cell_footprint": "sky130_fd_sc_ls__sdlclkp", |
| "cell_leakage_power": 13.44724, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 15.8386477, |
| "when": "!GATE&!SCE&CLK" |
| }, |
| { |
| "value": 14.6742014, |
| "when": "GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 13.3320404, |
| "when": "!GATE&SCE&!CLK" |
| }, |
| { |
| "value": 12.5250965, |
| "when": "!GATE&SCE&CLK" |
| }, |
| { |
| "value": 11.2314646, |
| "when": "GATE&SCE&!CLK" |
| }, |
| { |
| "value": 15.6846927, |
| "when": "!GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 13.8672354, |
| "when": "GATE&!SCE&CLK" |
| }, |
| { |
| "value": 10.4245501, |
| "when": "GATE&SCE&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.004554, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.004312, |
| "internal_power": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
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| 0.6667, |
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| 0.0210851, |
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| 0.0063892 |
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| }, |
| "max_transition": 1.5, |
| "min_pulse_width_low": 0.354361, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.004795 |
| }, |
| "pin,GATE": { |
| "capacitance": 0.002103, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.001985, |
| "internal_power": { |
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| 0.0251627 |
| ] |
| }, |
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| 0.0150993 |
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| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002221, |
| "timing": [ |
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| 0.3783835, |
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| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| 0.03125, |
| 0.0625, |
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| 0.75, |
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| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
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| 0.75, |
| 1.0, |
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| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x11": { |
| "index_1": [ |
| 0.01, |
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| 0.03903, |
| 0.05855, |
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| 0.13172, |
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| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1, |
| 1.5 |
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| "index_2": [ |
| 0, |
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| 0.25162, |
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| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
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| } |
| } |
