| { |
| "area": 31.968, |
| "cell_footprint": "sky130_fd_sc_ls__sdlclkp", |
| "cell_leakage_power": 0.05619244, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 0.0590551, |
| "when": "!GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.0545256, |
| "when": "GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0585856, |
| "when": "!GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.0589496, |
| "when": "!GATE&SCE&CLK" |
| }, |
| { |
| "value": 0.0545247, |
| "when": "GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.0541207, |
| "when": "!GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0548896, |
| "when": "GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.0548887, |
| "when": "GATE&SCE&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.004459, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.00422, |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
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| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
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| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
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| 0.0236084, |
| 0.0238236, |
| 0.0241462, |
| 0.0246302, |
| 0.0253563 |
| ] |
| }, |
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| 0.0091662 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "min_pulse_width_low": 0.166391, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.004697 |
| }, |
| "pin,GATE": { |
| "capacitance": 0.002194, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002062, |
| "internal_power": { |
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| 0.0292207, |
| 0.03013 |
| ] |
| }, |
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| 0.0177209, |
| 0.0180816, |
| 0.0186227 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002326, |
| "timing": [ |
| { |
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| 0.03125, |
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| [ |
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| 0.5024883, |
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| [ |
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| 0.4357565, |
| 0.5008607, |
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| 0.380418, |
| 0.4540671, |
| 0.5191713, |
| 0.5793926 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| 0.125, |
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| 0.75, |
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| 0.2672995, |
| 0.2677064, |
| 0.2644512 |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "fall_constraint,vio_10_10_1": { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
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| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
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| [ |
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| -0.1859883 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x13": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1, |
| 1.5 |
| ], |
| "index_2": [ |
| 0, |
| 0.00935, |
| 0.01402, |
| 0.02103, |
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| 0.15975, |
| 0.23963, |
| 0.35945, |
| 0.53917, |
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| ], |
| "values": [ |
| [ |
| 0.0230427, |
| 0.0100884, |
| 0.0040795, |
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