| { |
| "area": 27.1728, |
| "cell_footprint": "sky130_fd_sc_ls__sdlclkp", |
| "cell_leakage_power": 0.04731983, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 0.0489226, |
| "when": "!GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.0444185, |
| "when": "GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0484872, |
| "when": "!GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.0521479, |
| "when": "!GATE&SCE&CLK" |
| }, |
| { |
| "value": 0.0444173, |
| "when": "GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.044008, |
| "when": "!GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0480791, |
| "when": "GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.048078, |
| "when": "GATE&SCE&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.004371, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.004144, |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
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| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
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| 0.0229148, |
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| 0.0227692, |
| 0.0227554, |
| 0.0227346, |
| 0.0230254, |
| 0.0234617, |
| 0.0241161, |
| 0.0250977 |
| ] |
| }, |
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| 0.01735, |
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| 0.0088596, |
| 0.0096097 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "min_pulse_width_low": 0.161509, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.004598 |
| }, |
| "pin,GATE": { |
| "capacitance": 0.002273, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002153, |
| "internal_power": { |
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| 0.0282776, |
| 0.0288919, |
| 0.0298134 |
| ] |
| }, |
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| 0.0174147, |
| 0.0177671, |
| 0.0182958 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002394, |
| "timing": [ |
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| 0.03125, |
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| [ |
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| 0.4951641, |
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| [ |
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| 0.359666, |
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| 0.3779766, |
| 0.4491842, |
| 0.5142884, |
| 0.5720684 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.03125, |
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| 0.125, |
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| 0.75, |
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| 0.1562155, |
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| 0.2929342, |
| 0.2933411, |
| 0.2900859 |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "fall_constraint,vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
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| 0.5, |
| 0.75, |
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| [ |
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| [ |
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| [ |
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| [ |
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| -0.5054056, |
| -0.5644063 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
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| 0.25, |
| 0.5, |
| 0.75, |
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| [ |
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| -0.1835469 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x12": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1, |
| 1.5 |
| ], |
| "index_2": [ |
| 0, |
| 0.00788, |
| 0.01182, |
| 0.01773, |
| 0.0266, |
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| 0.08977, |
| 0.13466, |
| 0.20199, |
| 0.30299, |
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| ], |
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| [ |
| 0.011895, |
| 0.0023224, |
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| "related_pin": "CLK", |
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| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
