| { |
| "area": 25.5744, |
| "cell_footprint": "sky130_fd_sc_ls__sdlclkp", |
| "cell_leakage_power": 0.03532382, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 0.0364378, |
| "when": "!GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.0330672, |
| "when": "GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0368513, |
| "when": "!GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.0395237, |
| "when": "!GATE&SCE&CLK" |
| }, |
| { |
| "value": 0.0330667, |
| "when": "GATE&SCE&!CLK" |
| }, |
| { |
| "value": 0.0321652, |
| "when": "!GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 0.0357396, |
| "when": "GATE&!SCE&CLK" |
| }, |
| { |
| "value": 0.0357391, |
| "when": "GATE&SCE&CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.004142, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.003947, |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1.0, |
| 1.5 |
| ], |
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| 0.0198602, |
| 0.0197886, |
| 0.0196811, |
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| 0.0197212, |
| 0.0196547, |
| 0.019555, |
| 0.0196212, |
| 0.0197205, |
| 0.0198693, |
| 0.0200928 |
| ] |
| }, |
| "rise_power,hidden_pwr_template13": { |
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| 0.01735, |
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| 0.007109, |
| 0.007153, |
| 0.007219, |
| 0.0073178 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "min_pulse_width_low": 0.183479, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.004337 |
| }, |
| "pin,GATE": { |
| "capacitance": 0.002241, |
| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002097, |
| "internal_power": { |
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| 0.01735, |
| 0.02602, |
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| 0.023829, |
| 0.0239823, |
| 0.0240742, |
| 0.0242122, |
| 0.0244191, |
| 0.0247294 |
| ] |
| }, |
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| 0.01735, |
| 0.02602, |
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| 0.0150516, |
| 0.0150657, |
| 0.0150868, |
| 0.0151184, |
| 0.0151659 |
| ] |
| } |
| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002386, |
| "timing": [ |
| { |
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| 0.03125, |
| 0.0625, |
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| 0.5179505, |
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| [ |
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| 0.4166322, |
| 0.5000469, |
| 0.5749167, |
| 0.6424622 |
| ], |
| [ |
| 0.0905091, |
| 0.0972148, |
| 0.109015, |
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| 0.2986309, |
| 0.3942526, |
| 0.4776673, |
| 0.5525371, |
| 0.6213034 |
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| [ |
| 0.0766745, |
| 0.0833802, |
| 0.0951803, |
| 0.121222, |
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| 0.2860169, |
| 0.380418, |
| 0.4638327, |
| 0.5399232, |
| 0.6099102 |
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| [ |
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| 0.0744284, |
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| 0.4548809, |
| 0.5321921, |
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| 0.4508118, |
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| 0.3669902, |
| 0.450405, |
| 0.5277161, |
| 0.5977031 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.03125, |
| 0.0625, |
| 0.125, |
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| 0.75, |
| 1.0, |
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| 0.75, |
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| 1.25, |
| 1.5 |
| ], |
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| 0.266681 |
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| [ |
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| 0.2184714, |
| 0.2371888, |
| 0.2498027, |
| 0.2587546 |
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| 0.2078919, |
| 0.2266094, |
| 0.2392233, |
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| [ |
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| 0.2091126, |
| 0.2229473, |
| 0.2306784 |
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| 0.1773744, |
| 0.1948711, |
| 0.207485, |
| 0.2139954 |
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| 0.2522441, |
| 0.2660788, |
| 0.2786927, |
| 0.2852031 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "fall_constraint,vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
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| 0.5, |
| 0.75, |
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| [ |
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| [ |
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| [ |
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| -0.5937031 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| 0.01, |
| 0.03125, |
| 0.0625, |
| 0.125, |
| 0.25, |
| 0.5, |
| 0.75, |
| 1.0, |
| 1.25, |
| 1.5 |
| ], |
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| 0.25, |
| 0.5, |
| 0.75, |
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| [ |
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| [ |
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| -0.2030781 |
| ] |
| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x10": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
| 0.02602, |
| 0.03903, |
| 0.05855, |
| 0.08782, |
| 0.13172, |
| 0.19757, |
| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1, |
| 1.5 |
| ], |
| "index_2": [ |
| 0, |
| 0.00921, |
| 0.01381, |
| 0.02071, |
| 0.03106, |
| 0.04659, |
| 0.06989, |
| 0.10484, |
| 0.15726, |
| 0.23589 |
| ], |
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| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
