| { |
| "area": 25.5744, |
| "cell_footprint": "sky130_fd_sc_ls__sdlclkp", |
| "cell_leakage_power": 13.43398, |
| "clock_gating_integrated_cell": "latch_posedge_precontrol", |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "leakage_power": [ |
| { |
| "value": 14.9248827, |
| "when": "!GATE&!SCE&CLK" |
| }, |
| { |
| "value": 15.4357913, |
| "when": "GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 13.8870515, |
| "when": "!GATE&SCE&!CLK" |
| }, |
| { |
| "value": 11.9352679, |
| "when": "!GATE&SCE&CLK" |
| }, |
| { |
| "value": 11.4964118, |
| "when": "GATE&SCE&!CLK" |
| }, |
| { |
| "value": 16.7637495, |
| "when": "!GATE&!SCE&!CLK" |
| }, |
| { |
| "value": 13.4839837, |
| "when": "GATE&!SCE&CLK" |
| }, |
| { |
| "value": 9.5446637, |
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| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.004358, |
| "clock": "true", |
| "clock_gate_clock_pin": "true", |
| "direction": "input", |
| "fall_capacitance": 0.004226, |
| "internal_power": { |
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| 0.01735, |
| 0.02602, |
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| }, |
| "max_transition": 1.5, |
| "min_pulse_width_low": 0.152965, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.004491 |
| }, |
| "pin,GATE": { |
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| "clock": "false", |
| "clock_gate_enable_pin": "true", |
| "direction": "input", |
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| "internal_power": { |
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| }, |
| "max_transition": 1.5, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.00245, |
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| ] |
| }, |
| "related_pin": "CLK", |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
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| }, |
| "related_pin": "CLK", |
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| 0.03125, |
| 0.0625, |
| 0.125, |
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| 0.75, |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,GCLK": { |
| "clock_gate_out_pin": "true", |
| "direction": "output", |
| "internal_power": { |
| "fall_power,pwr_template13x10": { |
| "index_1": [ |
| 0.01, |
| 0.01735, |
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| 0.03903, |
| 0.05855, |
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| 0.29634, |
| 0.44449, |
| 0.6667, |
| 1, |
| 1.5 |
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| "index_2": [ |
| 0, |
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| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "statetable,CLK GATE SCE,M0": { |
| "table": [ |
| "L L L : - : L", |
| "L L H : - : H", |
| "L H L : - : H", |
| "L H H : - : H", |
| "H - - : - : N" |
| ] |
| } |
| } |
