| { |
| "description": "Full adder, inverted carry in.", |
| "file_prefix": "sky130_fd_sc_ls__fahcin", |
| "library": "sky130_fd_sc_ls", |
| "name": "fahcin", |
| "parameters": [], |
| "ports": [ |
| [ |
| "signal", |
| "COUT", |
| "output", |
| "" |
| ], |
| [ |
| "signal", |
| "SUM", |
| "output", |
| "" |
| ], |
| [ |
| "signal", |
| "A", |
| "input", |
| "" |
| ], |
| [ |
| "signal", |
| "B", |
| "input", |
| "" |
| ], |
| [ |
| "signal", |
| "CIN", |
| "input", |
| "" |
| ], |
| [ |
| "power", |
| "VPWR", |
| "input", |
| "supply1" |
| ], |
| [ |
| "power", |
| "VGND", |
| "input", |
| "supply0" |
| ], |
| [ |
| "power", |
| "VPB", |
| "input", |
| "supply1" |
| ], |
| [ |
| "power", |
| "VNB", |
| "input", |
| "supply0" |
| ] |
| ], |
| "type": "cell", |
| "verilog_name": "sky130_fd_sc_ls__fahcin" |
| } |