| { |
| "area": 43.1568, |
| "cell_footprint": "sky130_fd_sc_ls__edfxtp", |
| "cell_leakage_power": 0.0001853935, |
| "driver_waveform_fall": "ramp", |
| "driver_waveform_rise": "ramp", |
| "ff,IQ,IQ_N": { |
| "clocked_on": "CLK", |
| "next_state": "(D&DE) | (IQ&!DE)" |
| }, |
| "leakage_power": [ |
| { |
| "value": 0.0002211, |
| "when": "!D&CLK" |
| }, |
| { |
| "value": 0.0001516, |
| "when": "D&CLK" |
| }, |
| { |
| "value": 0.000169, |
| "when": "D&!CLK" |
| }, |
| { |
| "value": 0.0001999, |
| "when": "!D&!CLK" |
| } |
| ], |
| "pg_pin,VGND": { |
| "pg_type": "primary_ground", |
| "related_bias_pin": "VPB", |
| "voltage_name": "VGND" |
| }, |
| "pg_pin,VNB": { |
| "pg_type": "nwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VNB" |
| }, |
| "pg_pin,VPB": { |
| "pg_type": "pwell", |
| "physical_connection": "device_layer", |
| "voltage_name": "VPB" |
| }, |
| "pg_pin,VPWR": { |
| "pg_type": "primary_power", |
| "related_bias_pin": "VNB", |
| "voltage_name": "VPWR" |
| }, |
| "pin,CLK": { |
| "capacitance": 0.002221, |
| "clock": "true", |
| "direction": "input", |
| "fall_capacitance": 0.002105, |
| "internal_power": { |
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| ], |
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| ] |
| }, |
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| 0.0109385, |
| 0.0108151 |
| ] |
| } |
| }, |
| "max_transition": 5.0, |
| "min_pulse_width_high": 1.605716, |
| "min_pulse_width_low": 3.260234, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.002337 |
| }, |
| "pin,D": { |
| "capacitance": 0.00143, |
| "clock": "false", |
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| "fall_capacitance": 0.001399, |
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| 0.004944, |
| 0.0049424, |
| 0.00494 |
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| 0.0024411, |
| 0.0024201, |
| 0.0023885 |
| ] |
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| }, |
| "max_transition": 5.0, |
| "related_ground_pin": "VGND", |
| "related_power_pin": "VPWR", |
| "rise_capacitance": 0.001461, |
| "timing": [ |
| { |
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| [ |
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| 7.2285625, |
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| [ |
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| 6.9800817, |
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| [ |
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| 5.9885997, |
| 6.5221822, |
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| [ |
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| 3.5926305, |
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| 5.0142071, |
| 5.5441276, |
| 6.0777106, |
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| ], |
| [ |
| 3.073045, |
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| 5.1143048, |
| 5.6478873, |
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| [ |
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| [ |
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| 3.2534105, |
| 3.7808901, |
| 4.3120314, |
| 4.8456144, |
| 5.3779766 |
| ] |
| ] |
| }, |
| "related_pin": "CLK", |
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| [ |
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| 2.1363316, |
| 2.6003344, |
| 3.044806, |
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| [ |
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| [ |
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| 2.4249601, |
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| [ |
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| 2.2570455, |
| 2.6941929, |
| 3.1179124 |
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| [ |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "setup_rising", |
| "violation_delay_degrade_pct": 10 |
| }, |
| { |
| "clk_width": 4e-08, |
| "fall_constraint,vio_10_10_1": { |
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| ] |
| ] |
| }, |
| "related_pin": "CLK", |
| "rise_constraint,vio_10_10_1": { |
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| ] |
| }, |
| "sim_opt": "runlvl=5 accurate=1", |
| "timing_type": "hold_rising", |
| "violation_delay_degrade_pct": 10 |
| } |
| ] |
| }, |
| "pin,DE": { |
| "capacitance": 0.0026, |
| "clock": "false", |
| "direction": "input", |
| "fall_capacitance": 0.002465, |
| "internal_power": { |
| "fall_power,hidden_pwr_template13": { |
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| 0.0333333, |
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| 0.9878, |
| 1.48163, |
| 2.22233, |
| 3.33333, |
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| }, |
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